CHAPTER 1

Introduction


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1.3. Scope and outline

The main part of this thesis focuses on power, noise and accuracy of analog circuits. However, the working environment for the analog circuits treated here is a mixed level environment. To get the best performance, knowing the limits of power in digital and clearly defining the environment where analog should work is a must. In sub-micron digital CMOS, to optimize power dissipation, a low-power methodology applied at different levels of abstraction is necessary. Power in analog is related to noise and accuracy. A further investigation to quantify their inter-relationship is required. When accuracy is important, new solutions of increasing accuracy in modern CMOS have to be found. We are looking for solutions insensitive to second order effects like mobility reduction and velocity saturation capable of working at low voltage with high linearity, dynamic range and accuracy, with low-power consumption. The outline followed in this thesis is described below:

Chapter 2: Power considerations in sub-micron digital CMOS

Here, we consider first fundamental/physical limits and discuss afterwards the practical limits of power in digital, mostly at the architecture level. The fundamental limits are asymptotic limits and they cannot provide realistic comparisons between possible solutions. At architecture level, it is possible to find relations between power and signal to noise which provide a comparison basis to analog solutions. A new method is presented which takes into account different sources of quantization noise in fixed point representations. Because the computational power of an algorithm implemented in one chip solution dominates, we have considered the computational power. A simple example of a digital filter shows how power can be saved at the architecture level. The same filter has been realized in an analog way in Chapter 4 where comparisons to the digital approach are presented. Ways to low-power in digital are being discussed also. They will provide some input for the analog part of this thesis.

Chapter 3: Power considerations in sub-micron analog CMOS

In this chapter it is shown that low power analog circuits have to sacrifice dynamic range, linearity or accuracy. For analog functions, the reduction of supply voltages has a negative influence on dynamic range and power. In this chapter it is shown that low voltage is incompatible with low power when analog signal processing circuits are being considered. In plus, second order effects are becoming first order effects and analog solutions for higher supply voltages cannot be used anymore in scaled down processes. The main analog-related problems in scaled down processes are pointed out. In the beginning we are discussing fundamental limits of power in analog. They are combining in one simple equation power, S/N ratios and speed. There are no restrictions regarding topology, voltage swings, circuit topology, noise generated by active circuits, the process constants and linearity. Practical circuits show that power dissipation is dominated by the current needed to bias the active elements and has values few orders of magnitude larger than fundamental limits.

The next section will consider practical limits of power in analog used for comparing different solutions. In analog functions, power is needed for biasing and to have sufficient accuracy and dynamic range. A designer wants a certain dynamic range and speed with a given accuracy, gain and linearity. Power consumption can be noise related or accuracy related. As far as white noise is concerned it is proven that DR*Speed product is limited by power, topology and supply voltage regardless of the type of circuits: continuous time or sampled data, current-mode or voltage mode. This is a general method and can be applied to simple analog building blocks or to more complicated analog systems like filters in order to find noise related power. Compared to noise related power, accuracy related power makes use of Speed*Accuracy to find minimal power. The same conclusions like in noise driven power can be drawn for power supply scaled down processes.

Chapter 4: Gm-C integrators for low-power and low-voltage applications: A gaussian polyphase filter for mobile transceivers in 0.35mm CMOS

This chapter goes in circuits details showing how the theory described in Chapter 3 can be used for power comparisons. At low supply voltage, the key problem of analog signal processing functions is dynamic range reduction. Transconductors are basic functions in analog design used for amplifiers and filters. We are looking for power efficient architectures which can work at low supply voltages with high linearity and low noise. The new technologies are optimized towards digital applications and modern MOSTís suffer from velocity saturation and mobility reduction. New transconductor concepts which do not rely upon the ideal square law of a MOST, are needed. Another issue is to achieve large tunability without conflicting with the large swing requirement. We have presented two power efficient Gm-C integrators capable of working at low supply voltage with high linearity. The first integrator is an OTA-C integrator based on a new idea which features a constant window at the input for different tuning conditions. It allows 2V input swing from a 3.3V power supply voltage with high linearity. It is shown that large swings can be beneficial to achieve large DR/P ratios.

Positive feedback is a promising technique for enhancing gain in sub-micron CMOS because current matching in modern technologies improves. It avoids cascoding for having large gains and can be used for low-voltage applications. The second type of integrator considered in this chapter is a Gm-C integrator with local positive feedback for enhancing the gain. The reason for using this integrator consists in the low-voltage, high linearity and very high frequency of operation with a high power efficiency. It is compatible with standard digital technology has a high quality factor Q and can work down to 1.5V power supply voltage. Possible linearity improvements are shown. By using the DR*GBW product concept from Chapter 3 it is explained why the Gm-C approach has better power figures for the same working conditions when compared to OTA-C approach. The two integrators have been used to implement in an analog way the video filter used in Chapter 2. Matching in this type of filters is not important. Therefore we are dealing with noise driven power consumption. The required S/N of about 50dB shows that digital implementations have become more power efficient with possible improvement in the future, while analog solutions will have an increase in power due to power supply down scaling.

There are filter applications where matching requirements and noise requirements have the same importance, with constraints on power consumption and linearity. Channel selectivity in receivers has been realized until recently using SAW filters. Those components are external components and therefore integration on chip of selectivity has become a major concern in receivers. A polyphase filter is an example of a selective filter without the need of high Q bandpass sections which are power inefficient according to Chapter 3. Here selectivity is rather obtained by using polyphase signals where matching driven power consumption comes as a variable. Polyphase filters can discriminate between positive and negative frequencies and therefore, using this property, selectivity can be achieved. By using a low power integrator, we have shown how to realize a polyphase filter needed for image rejection in a mobile transceiver. It fits the specifications of a DECT receiver with much less power consumption than opamp based approaches.

Chapter 5: Chopping: a technique for noise and offset reduction

The flicker noise or 1/f noise has become of a major concern in analog circuits in deep sub-micron. In this chapter different methods to reduce 1/f noise and offset are being discussed. Chopping is a technique for noise and offset reduction employed to boost at the same time the accuracy and the dynamic range of analog circuits without extra penalty in power. As a modulation technique, chopping modulates in a different way white noise and 1/f noise of amplifiers. Therefore the difference between 1/f noise modulation and white noise modulation is being introduced with a comparison to sampling methods. Chopping is the only method which reduces 1/f noise and offset without modifying the baseband white noise like in the sampling case.

The trend in the new emerging applications is the increase of frequency range and data-rates. Chopping is a low frequency technique but there are applications where bandwidths of the signals are in the MHz range. At this frequency only the residual offsets generated from charge injection will limit the chopping frequency. A new method of using chopper modulation at high frequencies is introduced and a low-voltage, low-power, chopped transconductance amplifier for mixed analogue digital applications is presented. The principle can be used for a large class of analog circuits for mixed-signal designs. Further it is shown that by using chopping techniques and the chopped OTA presented in the beginning, the accuracy of a bandgap voltage reference can be improved about ten times with the benefit of reducing the 1/f noise of the reference. The two examples show that the term low power has to be related to the specific application and its own specs. The same building block namely an chopped OTA can need about 90 times more power when high-end specs are required.

Chapter 6: Low-noise, low residual offset, chopped amplifiers for high-end applications

In this chapter we investigate the possibility of reducing the charge injection residual offset and the increase of chopper frequency up to 10MHz. A chopper stabilized opamp can be used wherever offset and noise specifications are important. The chopped amplifiers presented in this chapter are primarily meant as amplifiers capable of driving headphones in portable digital audio with high power efficiency thanks to a class AB stage. The new idea and the key towards low residual offsets is chopping of a part of the bias current which is shared by the output stage and the OTA. We are considering also gain enhancement techniques to boost the gain and to improve the accuracy. In portable digital audio we need high dynamic ranges and high accuracy with minimum power. Two designs are introduced: a 0.8mm CMOS version and a 0.5mm CMOS version. The 0.5mm CMOS version can work at lower power supply voltages with larger gain, based on a new class AB stage. Measurements on the 0.8mm CMOS version shows a DR of 111dB and offsets lower than 100mV up to 7MHz chopper frequency.

Chapter 7: A 16-bit D/A interface with Sinc approximated semidigital reconstruction filter

This chapter shows that low-power techniques at the highest level of abstraction as architectural level can lead to power savings which cannot be obtained unless the complete system is taken into study. This chapter presents a 16-bit D/A interface as an example of a system where accuracy and noise give constraints on the power consumption. An important issue to be discussed here is the optimization of the number of coefficients. An FIR filter with a large number of coefficients needs a large number of additional digital circuitry increasing the area, power consumption and complicating more the clock distribution. A large number of coefficients, requires more shift registers. Power in the digital domain will increase. The accuracy of the coefficients is subject to process tolerance caused by rounding of the small coefficients and quantization to the process grid span. A large number of coefficients implies also big differences between coefficients and the accuracy of the smaller coefficients is impaired with consequences on the stop-band rejection.

By using a new method: Sinc approximation in the frequency domain and an iterative procedure one can reduce the number of coefficients taking into account process tolerances such that the out of band rejection of noise requirement is met. Compared to the standard solutions we have reduced about four times the number of the coefficients for the same requirements. A differential solution is proposed to reduce the digital crosstalk and to increase the output signal swing. An analysis of the matching, noise and clock jitter is provided. The D/A interface has been realized on chip in a 0.8mm CMOS, 5V technology and the measurement results are presented. Another approach: Sinc approximation method in the time domain shows that power can be shifted from the digital domain into analog domain which allows the best partitioning of the system in terms of power. The principle of the method is discussed and generalized. Using a combination of the two methods, it is shown that with the same filter complexity like in nowadays approaches a reduction of power with a factor four in the digital domain is possible. Chopping can be used again for high-end applications.


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