External Set-Up and Hold Times
Last Edit July 22, 2001
Overcoming Hold Time Error
Two options are available to overcome the problem of hold time error.
- Add one or more gates in PATH1 to offset the delay that has been
found in PATH2. Generally, a single gate will suffice (B1, a buffer).
(See Figure 6-6)
- Minimize the differences to an acceptable level through macro selection,
placement, load balancing and reduced metal lengths.
Figure 6-6 32-Bit Register: Two Clock Paths, Balanced Tree, Buffer
To compute the hold time of the design, the propagation delay of both
paths needs to be determined while factoring in the effects of tracking.
For the Q5000 Series, the effects are defined below.
For Like edges
- If like edges and like structures where they are placed on adjacent
cells on the same row or column, a 5% tracking is specified for AMCC
Q5000 and Q14000 arrays. The amount will vary with the array and with
the manner used by the vendor to specify tracking.
- If the two drivers are of the same macro type and they are placed
within the same quadrant, a tracking of 10% is specified for the AMCC
Q5000 and Q14000 arrays. Check with the vendor for the array to be used.
- If they are not the same macro but are placed within the same quadrant,
20% tracking is specified for the AMCC Q5000 and Q14000 arrays.
Check with the vendor for the array to be used.
The buffer B1 in Figure 6-6 adds delay to the data path to prevent
the hold time violation for th of macro FF16.
For unlike edges
Note: It is unlikely that two paths whose tracking in relation to each
other is of concern, would be placed in different quadrants. If they are,
consult with the array vendor.