Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White

 

Design Optimization

Last Edit July 22, 2001


Design To Reduce I/O Utilization

There are several techniques used to reduce the I/O cell utilization shown in Table 4-7.

Table 4-7 Reducing I/O Cell And Pad Utilization

Reducing I/O Utilization
Use the high-functionality interface macros.
Use bidirectional macros if possible.
Partition a system by bits (bit-slice) rather than function. This also allows the development of circuit sub-modules which reduce schematic capture and test efforts.
When speed requirements will permit it, use serial data transfer rather than parallel data transfer.
Multiplex test points to reduce test pinouts.
Multiplex non-critical outputs.
Transfer only one polarity of a signal on and off chip (single rail transfer) rather than differential if other factors permit it.
- use a VBB source and single-rail ECL.
Decode input signals on-chip.
Use local (to the array) counters; duplicate the counter on several arrays and synchronize.
Use bus architecture, where one or more I/O signals serve several signal sources.
Use external serial-input registers.

The difficulty with array-based circuit design is that, should a circuit require just one more I/O connection, there is no way to obtain it save by the selection of a larger array. There are no jumpers, piggy-backed components and other quick-and-dirty board design tricks that can apply. The I/O signal count must fit the target array, and be equal to or less than the available array signal pads.


 

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com

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