Structured Design Methodology
Last Edit July 22, 2001
The Design Submission Through Prototype
After processing by Implementation Engineering, the circuit will be submitted
for layout. Preplacement requests that were approved by the array vendor
are input to the layout system in this phase. For customers who wish a
particular package pin-out, a specific pad placement may be required.
Vendors attempt to honor these requests if they do not violate other placement
Placement restrictions may be I/O mode and package specific. They may
be driven by the type of macro, such as the dual-cell differentials. They
may be driven by MSI (multiple-cell) placement requirements, whether these
are hard or soft macros. Timing specifications and clock distribution
requirements are another factor as are the particular restrictions induced
by simultaneously switching outputs (SSO).
Packages that use internal power and ground planes may restrict where
added power and ground macros are placed, and this may conflict with the
All of these factors must be reviewed before approving a placement.
A placement is not usually considered final until after routing and then
only after the at-speed Back-Annotated simulation is approved by the customer.
On the average, a circuit requires a first-pass placement (90-95% auto-placement
is the goal) and some adjustments in a second pass.
- Intermediate Annotation
Some vendors may have an Intermediate-Annotation software package capable
of providing Manhattan-Distance algorithm-based Intermediate Annotation
delay files. They allow simulations to be performed with time delay data
that is much closer to reality than the generic, "every-same-sized-net-is-the-same-length"
For a circuit where the technology is being pushed to the limit, and
Back-Annotation will take more than a week to obtain, it might be a good
idea to run Intermediate-Annotation simulations. They are still not accurate
enough to be treated as a specification, but they could identify gross
errors in placement that could be corrected before routing.
Routing is the longer process. For circuits meeting the internal pin
count and cell utilization limits for the array, 95% of the nets can usually
be routed automatically. The last few are closed by a human operator at
a graphics interface terminal. Some array vendors will not accept an array
that cannot be 95% autorouted.
As a guideline, AMCCERC will report warnings for those circuits exceeding
recommended internal cell utilization limits and recommended internal
pin count limits. It will report an error for those circuits that exceed
the limits so far as to be considered impossible to route. It cannot cross-check
package pad-pin requirements or make any assumptions about the physical
location of the macros.
After layout, the Back-Annotation delay files are available to the designer
to rerun the logical and at-speed simulations, plus any of the optional
simulations originally submitted. These files provide the actual metal
lengths in the circuit nets as opposed to the estimated metal length,
and the actual (as far as is known) package pin capacitance for the output
Critical paths must be checked with this data. At this point, a failure
to meet specification timing requirements by a small amount may be correctable
with a layout adjustment or a routing change. Serious failures may signal
the need to re-design.
AMCC and most vendors guarantee the maximum worst-case Back-Annotation
at-speed simulation, i.e., guarantee that the silicon will not be slower
than the results.
The careful evaluation of the critical paths early in the design phase,
the proper derating of the fan-out loading, careful selection of the macros
and the options for those macros, preplacement for critical and sensitive
paths (balanced against the placement restrictions and rules for the array),
and the careful simulation and timing validation before layout, will all
ensure a successful design experience.
Re-simulation and timing validation after layout (place and route) help
ensure a successful wafer.
After the Back-Annotated simulations are approved by the customer, the
vendor can proceed to produce prototypes.
Array Design Acceptance
After prototyping and testing per the testing specification supplied
at design submission, including the functional vectors, the customer would
perform the final array acceptance as desired. At this point, full fabrication
of the final product can begin.