Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White

 

Introduction

Last Edit July 22, 2001


Design-Support Issues

Design Upgrades

A semi-custom array, full array or bit-slice design can be upgraded more easily than an LSI/MSI/SSI component or a fixed-instruction set microprocessor design.

For bit-slice, if the design enhancements are known at the time of the original design, allowances can be made through interconnections and functional capabilities that are not accessed until a microprogram accessing these features is incorporated. Many changes can be made with microprogram changes alone.

For semi-custom arrays, if the design enhancements are known in advance, the arrays can be partitioned to leave room for future macro additions or the macro functions could even be incorporated. As with bit-slice, the added capability is simply not accessed until required.

If the design enhancements (evolution) are not known, but are anticipated to occur, the allowances for expansion may be anticipated. The designer may provide room for the design changes to be incorporated onto the older schematics, with additional vectors to be added to the existing simulations. The design is thus easily revised.

Tradeoffs

The designer must evaluate the all the items discussed in this chapter to make a selection as to the best method of implementation for a specific circuit design. From there, the designer must further evaluate to find the best components available within the chosen category of implementation.


Exercises

1. To select a design approach, the following are questions that may need to be answered:

  • What architecture does the design require
  • What flexibility can be allowed in the implementation
  • What package types are desired versus what package types are available
  • What operating environment (Commercial, Industrial or Military)
  • What cooling considerations have been made (heat sinks, air flow)
  • What is the required interface to the outside world
  • What is the required I/O mode (ECL, TTL, CMOS, MIXED ECL/TTL)
  • What power supplies are available (+5, -5.2, -4.5,+5 with -4.5 or +5 with -5.2v)
  • How many of the required I/O signals are inputs
  • How many of the required I/O signals are outputs
  • How many of the required I/O signals are bidirectional
  • What type(s) of TTL: Totem pole, open collector or 3-stated
  • What type(s) of ECL: ECL 10K, ECL 100K, on-chip series termination, off-chip series termination, differential, open collector, Darlington, etc.
  • What about CML
  • What about CMOS
  • What are the physical size limitations imposed on the design
  • What word length is required for an adder, ALU, counter, sequencer
  • What instruction set or commands are to be supported
  • How big is the design (equivalent gates)
  • What is the intended maximum frequency of operation including I/O toggle frequency for the circuit, i.e., what are the performance requirements
  • How much design time has been allowed
  • What design support is available
  • How much debug time has been allowed
  • What debug support is available
  • What simulation support is available
  • What simulators
  • What timing verifiers
  • What about testability support
  • Are upgrades to the design planned and if so, how easily can a design be revised
  • What upgrades to the component series are planned
  • What are the possible time schedules for
    • design review:
    • design to prototype
    • prototype to production
  • What are the overall cost limitations


Review these questions. Catalog them as to design-specific, array-specific, component vendor-specific and workstation-specific. What other questions might need to be asked before a design implementation approach (semi-custom, full-custom, fixed components, bit-slice, or gate array) can be selected?

2. Review the latest issues of ASIC News and at least one other ASIC related magazine.

  1. Locate two articles on framework systems.
  2. Locate two articles on HDL and VHDL.
  3. Locate at least one survey on expected growth of demand for ASIC arrays: bipolar, BiCMOS, CMOS and GaAs.

 

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com




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