Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White



Last Edit July 22, 2001


The physical size limitations imposed on a design can dictate the design approach.

Base Arrays

Base arrays come in a variety of sizes, usually specified in terms of equivalent gates. The arrays discussed herein range from 250 to 28000 gates, depending on the computational approach used. Equivalent gates; allow a relative sizing between arrays of the same technology. The gate used as an equivalent gate for bipolar arrays is the NOR gate, that used for BiCMOS arrays is the NAND gate. Equivalent gate sizing can be misleading.

For a CMOS array, one gate is typically one cell. For the Q24000 Series BiCMOS arrays, one internal cell is approximately 4 equivalent gates.

Today's arrays are custom-designed to the project. The determination of the die size and the number of I/O is computed from initial evaluations based on the specification.


The actual cells; available on a bipolar array are larger and more complex, and can support a large variety of macros. A Q5000 Series logic cell (internal) can support: a 4:1 MUX, a 1:4 decoder, a scan-set D F/F, an 8-input OR/NOR, three latches or 2 D flip/flops. A 4-bit universal register (4 4:1 MUXs and 4 D flip/flops) requires 4.5 logic cells. A 4-bit carry-look-ahead adder with carry-out requires 5 logic cells. The 4-bit carry-look-ahead adder in the Q14000 Series BiCMOS arrays macro library requires 14 basic cells or 56 gates.

The Q20000 Series L-cell is sized based on one Turbo output; per cell and is smaller than a Q5000 cell. A flip/flop that uses 1 cell in the Q5000 Series may use 3 cells in the Q20000 Series. Estimating cell counts requires access to the macro library.

Basic sizing information such as cell counts and die sizes; can be obtained from the data sheets. Many circuit modules can be equated to cell counts by the specific array vendor. These estimates can be used for initial circuit sizing.

Array Size - Die Size

A full custom design may or may not be smaller in die size than a semi-custom design. For a heavily populated array, the differences may be insignificant. The comparison must be based on the specific application and the skill of the designer.


For arrays, the die size, the number of I/O pads, and the number of power and ground pads used affect available packaging;. A number of standard packages; are usually available for each array and the data sheet for an array series will provide the designer with an initial table of available packages. If less than the maximum number of I/O cells is used, some smaller packages may be usable.

The package selection; affects package pin capacitance;, which affects loading delay for output pins;, junction temperature; computations and cooling considerations;, and final cell placement;, which also depends on the pin capacitance, and should be made well before final design completion.

Word Length

The word length necessary for the system, whether a computer, controller, signal processor, etc., is known in advance. This is seen as the width of registers, partitioning of counters, width of adders, and number of simultaneously switching outputs; (SSO;s). It affects the partitioning and modularity of the design.

The adders; available with a macro library are typically 4-bit adders, cascadable with the carry-look-ahead; macro to build a range of standard adder sizes. With a macro design, the available MSI macros and SSI logic can be used to provide a range of non-standard word lengths.

Counters; are typically 4-bits wide, expandable to 12 or 16 bits in width. Comparators; are modulo 6. Registers; come as 4-bit widths and latches; as 8-bits (octal latch). Larger macros are also under development or custom structures may be possible.

Instruction Set

The instruction set; that the system is to support is another major impact on the design implementation selection. By building a custom or semi-custom array, the hardware can be configured to support any instruction set yet have the advantages of still being a VLSI solution.


The maximum frequency of operation; specified for the circuit must be compared to that available for the array series or the off-the shelf components. The nature of the design may make it necessary to look at the toggle frequency; of the internal functions.

The maximum frequency of operation, of interface as well as internal macros, is very important but it is not the only consideration when evaluating the performance that can be achieved. Due to loading delays, the final performance will depend heavily on the implementation possible with the given macros or possible custom macros, their drive factors; and load limits;.

Achievable speed is a function of both the
experience of the designer in general and
the macro library in specific.

As an example, three implementations of a test circuit were made with the Q3500 Series and they varied from 145MHz to 233MHz (worst case maximum speed limits).

The variance was found to be solely a function of the macros selected. This type of performance variance can be repeated for almost any circuit of any reasonable size. Speed, cell utilization (silicon density) and power can be traded off among the different possible implementations. This diversity is an advantage as well as a design challenge.

Macros - Libraries - Etc.

The existence of an extensive macro library;, or even one that supports the circuit function for the application at hand, can sway a decision as to which product to select.

For the arrays of interest, the designer needs to review the existence of a macro library. If the array has a macro library, review the macros available for application to the intended design.

Macro Library

In an array macro library;, macros; already released are available without delay. They represent pre-modeled, pre-simulated, pre-verified logic blocks. Their interconnect patterns are already defined for the various mask levels.

Custom Macros

If custom macros; are needed for a semi-custom array library, they involve 2-3 masks layers. If a custom macro has to be built for addition to a full custom array library, it is a multi-mask level design task.

Silicon Compilers

Silicon compilers provide a translation from a design description to pre-defined macros. They provide support for designers who wish to stay at a higher level in the design process. A silicon compiler can be compared to a software compiler it will speed the design process for the engineer at the cost of some flexibility.

Like framework systems, the industry has no set standard to measure or define exactly what a silicon compiler can do. They remain in isolated use, faced with the same resistance that software compilers met on their first introduction.

Other Support

Regardless of the design implementation;, a certain amount of software design support; is required. Error checking;, annotation;, simulation;, testability analysis;, fault-grading;, and vector rules checking; are some of the support areas pre-layout. After placement, there are placement rules checking, bus current checking for those arrays which require it, finalization of overhead current computations (for those arrays with programmable overhead), and finalization of power dissipation computations.


Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com

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