Last Edit July 22, 2001
Demand And Supply
The number of designers who can successfully complete the design of an
array-based circuit through design submission and prototype acceptance
is limited. Some estimates as of 1998 are as low as 50,000 engineers in
the USA. The demand for array-based circuit designers is already predicted
by the periodicals to exceed the supply of trained engineers.
The demand for designers capable of fast, efficient and successful design
with ASICs is exceeding the supply and the predictions for the future
show a projected shortage. In addition to adding engineers to meet the
demand, the productivity of each designer will need to be drastically
Designers must choose from a complex array of new products, new technologies,
changing standards, a wide range of support, changes in packaging, varied
design tools, and changing design rules, while evaluating cost-effectiveness
of the final product. Workstations are evolving, changing platforms, expanding
features, and moving from device to board to system level capabilites.
Note: While this book was being written, Daisy went from one of the leading
vendors to nothing, Valid transferred to the SUN platform, obsoleting
the SCALD system, hardware emulators were beginning to be interesting,
virtual memory was recognized as probably useful for the big designs,
the average array speed went from 280MHz to over 1.2Ghz, the ASIC array
size went from 1000 gates to over 100,000 gates (30,000 useable), and
design rules for the newer arrays were rated as four times more complicated
then before. In the time since, we have reached successful 750,000 gate
designs and higher, have reduced technology from 0.35 to 0.18 micron and
switched from schematic capture to Verilog or VHDL input. Design tools
have advanced to pick up the intermediate steps between the larger packages
and tools to remove manual operations and make on-screen design a reality.
Array vendors start as many FPGAs and ASICs and are outsourcing their
libraries. EDA houses are supplying libraries alsog with a full design
flow tools set, usually with the intention of being the sole vendor for
all of the array designer's needs.
With the size, simulations became longer and 4K vectors were no longer
a reasonable limit for test vectors, packaging was pushed to its limits
and beyond, simulators were faced with the need for hardware-assist, timing
verifiers became non-unique in the design cycle, frameworks began to be
spoken of if not heavily used, behavioral languages (HDL, VHDL) were accepted
in marketing vocabulary and then supported - and are now the accepted
design start. These changes are only some of the ongoing evolution made
over the past five years.
Pick up any magazine or newspaper devoted to ASIC and at least one article
will decry the monumental task facing the design engineer in the 90's
and forward. There is a constant need to acquire new skills, understand
and master new tools and accept new array design restrictions and features.
And not only is the designer faced with the choice of which vendor and
what product, but also with the management of the design once started.
The design tools that do exist may not work together making design management
a complex and error-prone process.
As with any new technology, the engineer can choose to study the product
and its support from the design manuals, datasheets and reading literature.
ASIC array vendors provide design manuals to assist the designer in completing
a successful design submission, that point of transfer between the design
and the vendor.
Vendors maintain applications support engineers to answer questions and
to guide the customer-designer through the submission process. This "earn
while you learn" is acceptable in some cases, where design schedules will
allow the weeks or months it takes for the engineer to "get up to speed"
and to redo those design phases that failed due to misunderstanding of
the technology and its limits.