The complete sequence of steps one has to go through to design a chip is generally referred to as a "design flow". This is when one starts a design from scratch. Although we focus on reuse in this book, design from scratch often needs to serve as a reference. Thus, it will be mentioned as such.
We already have stated that all Soft IP will eventually become Hard IP, suggesting that Hard IP reuse allows us to go directly to the back-end of a design or reuse flow. This might suggest to some an immediate savings in time and resources when comparing Soft IP versus Hard IP reuse.
However, such a statement would immediately and justly infuriate a Soft IP proponent, make a Hard IP proponent very happy, and serve only to create a situation in which the two perfectly legitimate engineering approaches could never again be viewed objectively. The fact is, both Hard IP and Soft IP reuse have strengths and weaknesses. Let us attempt to make an objective comparison. After all, it makes no sense to make a comparison between engineering approaches if it becomes an exercise in marketing for one of them. The number of steps and the time required to create the type of chip desired is only one aspect of comparison. It is an important one, but only one among many. Let's see what else we need to look at.
When comparing Soft and Hard IP reuse, some of the many points to examine are: risks, time-to-market, and predictability of time-to-market, flexibility in terms of how much freedom one has to choose the target technology, the flexibility in engineering changes one can make to a design to fit the new requirements, etc.
In fact, flexibility versus risks are often viewed as the two focal points for comparison.
Of course, it is very important not to take such a limiting view when comparing these two engineering approaches. We have already seen in the discussions in previous chapters, especially when talking about optimization, that there are many not so obvious factors to consider. There are also issues such as tool costs and the type of engineering talent required, which arc much different for the two approaches. Of the many points of comparison, we will hopefully touch upon the most important subset.
Soft IP reuse offers a very high level of flexibility. This flexibility alone may be enough reason for some to take that path. Engineers especially love that flexibility. However, the high degree of flexibility often brings with it the highest level of uncertainty, especially for Soft IP reuse, in terms of the timing of the physical layout. When comparing Soft IP reuse with design from scratch, it seems obvious that chips, designed from scratch starting with only a very high-level functional description of what one expects from a chip, will require the highest level of resources. For a design from scratch, simulation and test vectors also need to be generated, while for Soft IP reuse they can generally be reused. A high-fault coverage for fault simulation is required in order to get acceptable assurances that a chip actually works as needed. This can be a time-consuming, expensive task that does not really guarantee a working chip for reasons too test-specific to be discussed here. Thus, again our conclusion is that a sensible IP reuse methodology can mean substantial savings in resources. The quality of the simulation and lest suiles is already established and the desired performance can often be achieved by simply migrating to a higher performance process.
Hard IP reuse offers considerably less flexibility than Soft IP reuse. This lack of flexibility often leads to an immediate rejection of the idea of Hard IP reuse. However, this lack of flexibility also has positive aspects. It eliminates potential functional errors and minimizes highly probable timing errors in a Hard IP reused part. We also have seen just how much can actually be accomplished with postlayout optimization. This alone should convince the rather biased synthesis world to look at compaction, the methodology used for Hard IP, to see its merit as a valuable complement to Soft IP methodologies. For Hard IP reuse, there are limitations to being able to benefit from some drastic topological changes from process to process, such as additional layers of metal. Furthermore, there arc very limited means for changing any functionality of a reused Hard IP. Of course, if functional changes arc made to Soft IP, many of the advantages of Soft IP reuse also arc lost. In Hard IP, floorplans, aspect ratios of blocks can not be changed, or only in a very limited way.
Thus, an open mind and some willingness to make some compromises are required in order to benefit from both Soft and Hard IP reuse and get better, faster, less expensive and more predictable results.
In a nutshell, with Soft IP reuse, we preserve the functionality at the expense of flexibility but can get more flexibility at the expense of guaranteed functionality. We can not very well predict the timing of reused Soft IP in DSM technologies.
With Hard IP reuse, we preserve functionality at all times and the timing most of the time. If the timing is off somewhat, it is easy to fix with the additional benefit of optimizing the reused Hard IP with respect to liming, power, signal integrity and area as a postlayout step.
Cost, performance, risks, and time-to-market requirements are some of the factors that influence the decision about which blocks to reuse as Soft IP and which to migrate as Hard IP. For reuse of a certain existing IP, an objective evaluation of the state of this IP is required. We already know one very important positive point: we know that the existing circuit works, it has a proven track record. It takes a very objective approach to decide if the design is sound otherwise. Is the architecture still up to date? Does it have the required levels of testability? Is the test coverage satisfactory? The questions that need to be asked are highly contingent on the application of the circuit. The questions also depend again on whether the retargeting is done as Soft IP or Hard IP.
This evaluation is often also a real challenge between management
and engineers. Engineers always want and know ways in which to
"improve" a circuit no matter how well it works. They feel stifled by
reuse, by the apparent inability to reenginecr a system, especially for
Hard IP reuse.
The deciding engineers are also often front-end, high-level, architectural, creative types. They don't think of back-end, layout optimization. The engineer's top priority is to create the most elegant solution with the highest possible performance. On the other hand, management generally leans more towards issues such as minimizing cost, minimizing or guaranteeing time-to-market with "good enough" performance.
When designing an entire system, there are usually at least some circuits that need not and should not be redesigned, and that is key. Reuse what can be reused and redesign what needs to redesigned. Besides, progress in processing technology is so incredibly fast that the time between newer, more aggressive processes is so short that obsolescence often has not had time to become a major issue in the design philosophy used for reusable IP.
Having looked at some of the ideas concerning redesign versus reuse, we need to look at the costs, risks and time issues in more detail. Trying to maximize the useful lifetime of a well designed, field-proven chip is one of the key motivators for Hard IP reuse. Just where the boundary lies between doing a redesign versus reuse will have to be determined by evaluating the cost/performance/time-to-market benefits and trade-offs.
As we mentioned, this chapter discusses both, Soft and Hard IP, but the discussion will be limited mostly to comparing the two methodologies and pointing out the complementary values of Soft and Hard IP.
We still have not addressed the question of what types of circuits are the best candidates for reuse. Performance of circuits, questions of costs, and silicon usage are all very strongly influenced by the way a chip is laid out and what design methodology was used. Full custom design allows for the ultimate attention to the chip layout, but the cost of full custom design may be prohibitive. However, the large initial investment for a full custom design is also one of the most important arguments for reuse. After looking at design and reuse flows with the associated cost and risk factors throughout these chapters, we will be in a better position to judge. It would certainly be nice to be able to amortize the high initial investment for a sophisticated VLSI design over more than one generation of processing technology through IP reuse and, in particular, Hard IP reuse.