With the introduction of 0.18 micron CMOS process technology, a new phenomenon in circuit manufacturing becomes more important than when minimum layout dimensions were larger:
Design rule values as specified in design rule manuals arc no longer “hard” numbers. Actually, anybody who has worked with foundries knows that they never were. There were always “gray” areas, but these issues were not that critical with the larger layout dimensions of the previous processes. For older processes, designers and EDA tool developers considered process rule values as strict limits when creating mask layouts. Now, such “fixed” process rules have been replaced by “preferred” process rules. They have turned into gray areas around the specified rule values. This concept is illustrated in Figure 3.9 [16, 17]
Fig. 3.9 The Gray Areas Leading to Preferred Design Rules
For the shrinking layout dimensions of DSM processes, the choice of design rule values is increasingly pushed towards the high end of the yield range. Choosing a larger value guarantees a higher yield for a particular rule, but it results in less dense designs. A lower rule value means the opposite: Manufacturing yield will be less, but designs are denser. Many foundries now also specify a preferred design rule value together with the minimum allowable rule value. If preferred values are used wherever space permits in the final layout, a substantially higher manufacturing yield can be obtained.
A necessary design strategy for DfM in DSM processes is to avoid implementing minimum design rule values wherever possible. The minimum allowable design rule values should only be used when design density and substantial loss in performance are at stake. In Chapter 2, we discussed the critical path data resulting from compaction. This type of data can be very useful here. The drawback on yield will only pay off against using larger rule values along the critical path that determines block dimensions. Of course, this is because using larger rule values: on the critical path will result in a larger silicon area on the design, which will lead to a higher cost of silicon and reduced yield because of a larger die size. Other than chip or block size, the critical path does not address penalties in terms of performance. Performance may be an even more critical parameter than chip area.
At all locations thai are not dimensionally critical in the final mask layout, larger than minimum rule values should be respected. If implemented properly and consequently, a defect falling randomly on the wafer during fabrication simply has less of a chance of producing a fatal circuit malfunction. In addition, mask layout postprocessing before manufacturing, such as optical proximity correction and the use of phase shifting masks, will be facilitated.
Introducing nonminimum rule values in the design is not something that can be implemented by the foundry after tapeout. The consequences in terms of design performance and functionality are too great for that. The implementation of preferred rules will have to be an integral part of the design flow for enhanced manufacturability. Only (hen is the designer able to fully verify the final design, including the consequences of something such as using a wire-spreading tool on the final routing of standard cell blocks.
How can such preferred design rules be implemented?
It is obvious that automation is needed to implement larger than minimum design rule values effectively and efficiently. If the fact that certain preferred rule values are more preferred than others - because of a difference in yield gain - is added to the complexity of the problem, it becomes clear that a manual approach to the problem is doomed to produce suboptimal results. In addition, it will consume too much in terms of precious human resources.
EDA tools for implementing nonminimum rule values should assist designers in the following areas:
When routing a design, the distances between adjacent wires should be made nonminimum wherever possible. This is not feasible when constructing the routing. If nonminimum rules were used at that stage, many signals would end up not being connected. Instead, postprocessing of the routed design has to be done, known as wire-spreading. We have already showed this in Figure 3.8.
Custom cell creation is still very much dominated by manual layout design, whether for standard cells or regular blocks like memories. Again, introducing nonminimum spacing while drawing the layout is a highly complex task. Designers will face a high risk of having to “create space” to get that cell to fit its required footprint. The step of introducing nonminimum rules in a custom cell layout should be a postprocessing task following fully custom layout design. This will allow designers to focus on the main task of creating the densest possible cell layout.
The enhancement of layout to ensure better manufacturing yield can be automated by using layout compaction software, because a compactor is able to reposition each individual polygon edge in order to produce a design that is correct in terms of the design rules. Optimization for yield is done by analysis of the layout for the available “freedom of movement” at each polygon edge. The available space for each polygon edge will then be prioritized to get the highest return on yield enhancement. This is similar to the concept of “critical areas,” discussed in the last paragraph.
Design rules are defined when designing a new process. It is the process engineer's task to pick a suitable number in the manufacturability range measured for each rule. A full evaluation of the consequences of choosing a particular set of rule values is a far from trivial task. Essentially, it requires the construction of test designs that use the proposed rules optimally. Layout compaction software can help in this respect, due to its ability to quickly implement a set of new minimum (and preferable) design rule values on a collection of given test designs. This allows a proper trade-off of manufacturing yield and design density to already be made in the process definition stage.
Design verification for DfM is the last stage requiring EDA tool assistance. A manufacturability analysis of a particular cell that highlights the hot spots for yield is needed, in addition to DRC and LVS reports. Ideally, locations would be flagged where minimum rule values are unnecessarily used.
In summary, the use of nonminimum design rule values will be an important aspect of DfM for manufacturability in future DSM processes. Layout compaction and wire-spreading tools clearly help to implement preferred design rule values on mask layouts for enhanced manufacturability. Since this area of DfM is still quite a new concept, areas such as verification for manufacturability still need to be further explored.
The number of point defects in IC layouts is related to the surface area of a chip. This is of course evidenced by the fact that increasingly larger chips could only be manufactured as the technology matured and the industry learned how to lower defect densities over the years. However, studies have shown that not all areas on a chip are equally probable of having defects. In addition, even if present, defects do not cause failures equally in all areas. For instance, if there is no circuitry present where a defect occurs, it will probably not cause a chip failure.
Areas that are more prone to defects are often referred to as critical areas . Accordingly, minimizing the dimensions of such critical areas will increase manufacturing yield. Compaction is the process for minimizing such areas.
Thus, a compactor coupled with an algorithm that requires the compaction of areas on a chip only where the defect density is expected to be high, while at the same time respecting circuit process rules and performance criteria of the circuit.
The first significant work in this area dates back to just 1992  and our discussion has been stimulated by work presented at DATE 2000 . With the rapidly growing complexity of DSM VLSI designs, this is a critical area to be further studied.
Of course, it is discussed here because DfM is becoming quite a hot issue and the focus of the present work on application areas of compaction. It is clearly an additional and interesting application area whose importance is bound to grow significantly with larger and denser chips.