As processing technology evolves, as layout dimensions get smaller and chips larger and as interconnects start to dominate performance, design practices need to change. Some of the cherished and established measures of good design quality may no longer be valid. For this discussion, we examine some of the considerations which are to be kept in mind, some changes in design philosophy that might be beneficial, as processing technology moves from pre-DSM to DSM technologies. The discussion will not focus on ideas on how make Hard IP reuse easy. These design guidelines for making retargeting easier will be discussed Chapter 5.
We have already discussed the primary focus for obtaining a well designed chip and making it as fast as possible for pre-DSM technologies. Speed is determined by good design principles, such as optimally dimensioning the transistors, and a small chip size is achieved with an optimal layout. The rest is a question of the minimally allowed layout dimensions for certain transistor geometries as determined by the processing technology used. It was perfectly acceptable to ignore metal interconnects as a timing factor except perhaps for clock lines. The interconnect dimensions and their layout were only critical for layout density and current carrying capability.

With a bias toward examining only issues that affect the physical layout, a key issue has always been to develop as small a chip as possible for a certain function. With this in mind, some of the well established techniques for achieving good, small pre-DSM designs, and some of their benefits are:

  1. Smaller chips meant more chips per wafer, better yield because of the area-related defect density and smaller, less expensive packaging.
  2. Smaller chips could be achieved through logic minimization. Logic minimization decreased the number of gates and the number of active devices for a given function. Smaller numbers of active devices achieved through logic minimization meant smaller parasitics and more speed.
  3. Smaller chips could be achieved through floorplanning that made the blocks fit nicely together, as closely as possible. If this resulted in longer interconnects, it was not a problem. Problems that had to be considered were an inability to route due to a bad floorplan, too many vias introducing parasitics and affecting the yield and other issues. Again, we know that we need to review these guidelines.

In summary: Minimizing chip size and device count were key issues.

Priorities have changed for today's DSM technologies. Placing more active circuitry on a chip is inexpensive and easy to do. If the result is shorter interconnects, it is well worth it. Consequendy, everything possible should be done to shorten on-chip interconnects for today's DSM technologies and, where necessary, balance them even for nonclock lines.

If interconnects can be shortened due to an increase in some hundred additional “unnecessary” active devices on multimillion transistor chips, it is a rather small price if they do not significantly increase power consumption. Some of these old, proven methods of design optimization such as logic minimization may actually lead to an unwanted and unnecessary loss in circuit performance. Some more sensible design guidelines that take DSM effects into account should be followed, such as:

  1. The very small active devices take up much less space than the routing. We already suggested that logic minimization might not Jead to the best floorplan and the best design. For instance, parallelism of certain functions may lead to shorter interconnecting wires.
  2. Placing blocks too closely together may result in routing difficulties, requiring a lot of ripping up and rerouting and prolonging the design process or increasing wire length. This is particularly critical since routing is already one of the most time-consuming steps. Also, it could force the router to switch metal layers too often to complete the routing, resulting in too many vias with high parasitics affecting speed and lowering chip yield.
  3. Squeezing together metal lines to save routing space may negatively affect signal integrity as a result of on chip cross-talk, increase capacitive loading which slows down the chip, increase dynamic power consumption and create yield problems due to bridging. Besides, narrow metal lines to save space will increase parasitic resistance, lowering available voltage at the active devices and may add electromigration problems.

In summary: Everything possible within reason should be done to shorten interconnects and keep some of them from being to close to each other.


Figure 1.1 shows a high-level conceptual image of Hard IP retargeting. We discuss the required inputs and the details of what is required to migrate various layout structures and what we can expect as outputs in Chapter 2.

Fig. 1.1 Hard IP Retargeting


We mentioned that we may use a linear shrink or compaction for migrating a chip to a different process. Since one of the major goals of migration is to reuse existing designs with a minimum amount of rework, we would like certain characteristics of the Hard IP to remain unchanged or to change undramatically and predictably. Of course, we do want the IP performance to improve.

If we can show that functionality is not affected by retargeting, that the IP speed improves and that minor changes in relative timing are such that the IP still works after migration, we will have achieved the main goals of IP reuse.

For the functionality of a chip to remain unchanged through migration, the netlist must remain unchanged. The netlist remains the same if the topology of a layout remains unchanged through the migration step. Clearly, the remapping accomplished with the migration process does not change the topology of a circuit. For instance, a polygon edge to the left of another polygon edge before the migration process will be positioned either closer or farther from this polygon edge, but still to the left after migration. This means the netlist remains unchanged and the functional behavior of a circuit before migration equals the functional behavior of a circuit after migration.

The relative timing on a chip is the most critical aspect enabling a chip to work correctly. Relative timing concerns the timing relationship between the edges, the transitions of the signals. Parameters such as setup and hold times are directly dependent on relative timing. For a linear shrink, all layout dimensions, the dimensions of the active parts as well as the interconnects, change by the same proportionality factor. The relationships, the ratios between the layout geometries such as interconnect lengths and widths, transistor areas, do not change. This suggests that the physical layout-dependent relative timing relationships do not change either because they depend on geometrical ratios. The absolute timing changes but the relative timing should not. For compaction, a nonlinear shrink, changes in relative timing can not be completely avoided but they can be kept to a minimum. This will be very helpful when an existing layout with blocks and routing is migrated as an entity.

Based on these observations, the ratios in the relationships between the lengths and widths of interconnects, routed or otherwise, also remain largely unchanged. This produces enormous benefits by preserving relative timing on chips being migrated. The significance of this can not be overestimated and it will increase substantially as the DSM technology gets deeper. This issue is examined in more detail in Chapter 2.

Finally, absolute timing is the measure for the speed performance of a chip. It is the absolute timing that determines the maximum clock rate of a digital circuit. We want it to change in migration and it does.

In all of the following discussions, we will attempt to speed up the absolute timing, preserve the relative timing of workable chips and fix with layout manipulations any undesired signal skews that might have been introduced by migration or might even have existed in the old chip.