ASICs Chapter 11: Verilog HDL

Back to index of chapters

CHAPTER 11
VERILOG HDL

In this chapter we look at the Verilog hardware description language. Gateway Design Automation developed Verilog as a simulation language. The use of the Verilog-XL simulator is discussed in more detail in Chapter 13. Cadence purchased Gateway in 1989 and, after some study, placed the Verilog language in the public domain. Open Verilog International (OVI) was created to develop the Verilog language as an IEEE standard. The definitive reference guide to the Verilog language is now the Verilog LRM, IEEE Std 1364-1995 [1995]. 1 This does not mean that all Verilog simulators and tools adhere strictly to the IEEE Standard--we must abide by the reference manual for the software we are using. Verilog is a fairly simple language to learn, especially if you are familiar with the C programming language. In this chapter we shall concentrate on the features of Verilog applied to high-level design entry and synthesis for ASICs.

 

11.1   A Counter

11.2   Basics of the Verilog Language

11.3   Operators

11.4   Hierarchy

11.5   Procedures and Assignments

11.6   Timing Controls and Delay

11.7   Tasks and Functions

11.8   Control Statements

11.9   Logic-Gate Modeling

11.10   Modeling Delay

11.11   Altering Parameters

11.12   A Viterbi Decoder

11.13   Other Verilog Features

11.14   Summary

11.15   Problems

11.16   Bibliography

11.17   References


1. Some of the material in this chapter is reprinted with permission from IEEE Std 1364-1995, © Copyright 1995 IEEE. All rights reserved.




Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy Advertise