10.12  Arithmetic

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10.12  Arithmetic

The following example illustrates type checking and type conversion in VHDL arithmetic operations [VHDL 93LRM7.3.4-7.3.5]:

entity Arithmetic_1 is end; architecture Behave of Arithmetic_1 is
        begin process
        variable i : INTEGER := 1; variable r : REAL := 3.33;
        variable b : BIT := '1';
        variable bv4 : BIT_VECTOR (3 downto 0) := "0001";
        variable bv8 : BIT_VECTOR (7 downto 0) := B"1000_0000";
        begin 
--              i := r;            -- you can't assign REAL to INTEGER. 
--              bv4 := bv4 + 2;    -- you can't add BIT_VECTOR and INTEGER.
--              bv4 := '1';        -- you can't assign BIT to BIT_VECTOR.
--              bv8 := bv4;        -- an error, the arrays are different sizes.
r               := REAL(i);        -- OK, uses a type conversion.
i               := INTEGER(r);     -- OK (0.5 rounds up or down).
bv4             := "001" & '1';    -- OK, you can mix an array and a scalar.
bv8             := "0001" & bv4;   -- OK, if arguments are the correct lengths.
wait; end process; end;

The next example shows arithmetic operations between types and subtypes, and also illustrates range checking during analysis and simulation:

entity Arithmetic_2 is end; architecture Behave of Arithmetic_2 is
type TC is range 0 to 100;                                                                                                                              -- Type INTEGER.
type TF is range 32 to 212;                                                                                                                             -- Type INTEGER.
subtype STC is INTEGER range 0 to 100;                                                                                                                          -- Subtype of type INTEGER.
subtype STF is INTEGER range 32 to 212;                                                                                                                                 -- Base type is INTEGER.
begin process 
variable t1 : TC := 25;   variable t2 : TF := 32;
variable st1 : STC := 25; variable st2 : STF := 32;
begin 
--              t1              := t2;            -- Illegal, different types.
--              t1              := st1;           -- Illegal, different types and subtypes.
                st2             := st1;           -- OK to use same base types. 
                st2             := st1 + 1;       -- OK to use subtype and base type.
--              st2             := 213;           -- Error, outside range at analysis time.
--              st2             := 212 + 1;       -- Error, outside range at analysis time.
                st1             := st1 + 100;     -- Error, outside range at initialization.
wait; end process; end;

The MTI simulator, for example, gives the following informative error message during simulation of the preceding model:

# ** Fatal: Value 25 is out of range 32 to 212
#    Time: 0 ns  Iteration: 0  Instance:/
# Stopped at Arithmetic_2.vhd line 12
# Fatal error at Arithmetic_2.vhd line 12

The assignment st2 := st1 causes this error (since st1 is initialized to 25).

Operations between array types and subtypes are a little more complicated as the following example illustrates:

entity Arithmetic_3 is end; architecture Behave of Arithmetic_3 is
type TYPE_1 is array (INTEGER range 3 downto 0) of BIT;
type TYPE_2 is array (INTEGER range 3 downto 0) of BIT;
subtype SUBTYPE_1 is BIT_VECTOR (3 downto 0);
subtype SUBTYPE_2 is BIT_VECTOR (3 downto 0);
begin process
variable bv4 : BIT_VECTOR (3 downto 0) := "0001";
variable st1 : SUBTYPE_1 := "0001"; variable t1 : TYPE_1 := "0001";
variable st2 : SUBTYPE_2 := "0001"; variable t2 : TYPE_2 := "0001";
begin 
                bv4 := st1;                -- OK, compatible type and subtype.
--              bv4 := t1;                 -- Illegal, different types.
                bv4 := BIT_VECTOR(t1);     -- OK, type conversion.
                st1 := bv4;                -- OK, compatible subtype and base type.
--              st1 := t1;                 -- Illegal, different types.
                st1 := SUBTYPE_1(t1);      -- OK, type conversion.
--              t1  := st1;                -- Illegal, different types.
--              t1  := bv4;                -- Illegal, different types.
                t1  := TYPE_1(bv4);        -- OK, type conversion.
--              t1  := t2;                 -- Illegal, different types.
                t1  := TYPE_1(t2);         -- OK, type conversion.
                st1 := st2;                -- OK, compatible subtypes.
wait; end process; end;

The preceding example uses BIT and BIT_VECTOR types, but exactly the same considerations apply to STD_LOGIC and STD_LOGIC_VECTOR types or other arrays. Notice the use of type conversion, written as type_mark'(expression), to convert between closely related types. Two types are closely related if they are abstract numeric types (integer or floating-point) or arrays with the same dimension, each index type is the same (or are themselves closely related), and each element has the same type [VHDL 93LRM7.3.5].

10.12.1  IEEE Synthesis Packages

The IEEE 1076.3 standard synthesis packages allow you to perform arithmetic on arrays of the type BIT and STD_LOGIC . 1 The NUMERIC_BIT package defines all of the operators in Table 10.16 (except for the exponentiating operator '**' ) for arrays of type BIT . Here is part of the package header, showing the declaration of the two types UNSIGNED and SIGNED , and an example of one of the function declarations that overloads the addition operator '+' for UNSIGNED arguments:

package Part_NUMERIC_BIT is
type UNSIGNED is array (NATURAL range <> ) of BIT;
type SIGNED is array (NATURAL range <> ) of BIT;
function "+" (L, R : UNSIGNED) return UNSIGNED;
-- other function definitions that overload +, -, = , >, and so on.
end Part_NUMERIC_BIT;

The package bodies included in the 1076.3 standard define the functionality of the packages. Companies may implement the functions in any way they wish--as long as the results are the same as those defined by the standard. Here is an example of the parts of the NUMERIC_BIT package body that overload the addition operator '+' for two arguments of type UNSIGNED (even with my added comments the code is rather dense and terse, but remember this is code that we normally never see or need to understand):

package body Part_NUMERIC_BIT is
constant NAU : UNSIGNED(0 downto 1) := (others =>'0'); -- Null array.
constant NAS : SIGNED(0 downto 1):=(others => '0'); -- Null array.
constant NO_WARNING : BOOLEAN := FALSE; -- Default to emit warnings.
function MAX (LEFT, RIGHT : INTEGER) return INTEGER is
begin -- Internal function used to find longest of two inputs.
if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end MAX;
function ADD_UNSIGNED (L, R : UNSIGNED; C: BIT) return UNSIGNED is
constant L_LEFT : INTEGER := L'LENGTH-1; -- L, R must be same length.
alias XL : UNSIGNED(L_LEFT downto 0) is L; -- Descending alias,
alias XR : UNSIGNED(L_LEFT downto 0) is R; -- aligns left ends.
variable RESULT : UNSIGNED(L_LEFT downto 0); variable CBIT : BIT := C;
begin for I in 0 to L_LEFT loop -- Descending alias allows loop.
RESULT(I) := CBIT xor XL(I) xor XR(I); -- CBIT = carry, initially = C.
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop; return RESULT; end ADD_UNSIGNED;
function RESIZE (ARG : UNSIGNED; NEW_SIZE : NATURAL) return UNSIGNED is 
constant ARG_LEFT : INTEGER := ARG'LENGTH-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG; -- Descending range.
variable RESULT : UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin -- resize the input ARG to length NEW_SIZE
        if (NEW_SIZE < 1) then return NAU; end if; -- Return null array.
        if XARG'LENGTH = 0 then return RESULT; end if; -- Null to empty.
        if (RESULT'LENGTH < ARG'LENGTH) then -- Check lengths.
                RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
        else -- Need to pad the result with some '0's.
                RESULT(RESULT'LEFT downto XARG'LEFT + 1) := (others => '0'); 
                RESULT(XARG'LEFT downto 0) := XARG;
        end if; return RESULT;
end RESIZE;
function "+" (L, R : UNSIGNED) return UNSIGNED is -- Overloaded '+'.
constant SIZE : NATURAL := MAX(L'LENGTH, R'LENGTH);
begin -- If length of L or R < 1 return a null array.
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU; end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0'); end "+";
end Part_NUMERIC_BIT;

The following conversion functions are also part of the NUMERIC_BIT package:

function TO_INTEGER (ARG : UNSIGNED) return NATURAL;
function TO_INTEGER (ARG : SIGNED) return INTEGER;
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED;
function RESIZE (ARG : SIGNED; NEW_SIZE : NATURAL) return SIGNED;
function RESIZE (ARG : UNSIGNED; NEW_SIZE : NATURAL) return UNSIGNED;
-- set XMAP to convert unknown values, default is 'X'->'0'
function TO_01(S : UNSIGNED; XMAP : STD_LOGIC := '0') return UNSIGNED;
function TO_01(S : SIGNED; XMAP : STD_LOGIC := '0') return SIGNED;

The NUMERIC_STD package is almost identical to the NUMERIC_BIT package except that the UNSIGNED and SIGNED types are declared in terms of the STD_LOGIC type from the Std_Logic_1164 package as follows:

library IEEE; use IEEE.STD_LOGIC_1164.all;
package Part_NUMERIC_STD is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
end Part_NUMERIC_STD;

The NUMERIC_STD package body is similar to NUMERIC_BIT with the addition of a comparison function called STD_MATCH , illustrated by the following:

-- function STD_MATCH (L, R: T) return BOOLEAN;
-- T = STD_ULOGIC UNSIGNED SIGNED STD_LOGIC_VECTOR STD_ULOGIC_VECTOR

The STD_MATCH function uses the following table to compare logic values:

type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN;
constant MATCH_TABLE : BOOLEAN_TABLE := (
---------------------------------------------------------------------
-- U     X     0     1     Z     W     L     H     -
---------------------------------------------------------------------
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE), -- | U | 
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE), -- | X | 
(FALSE,FALSE, TRUE,FALSE,FALSE,FALSE, TRUE,FALSE, TRUE), -- | 0 | 
(FALSE,FALSE,FALSE, TRUE,FALSE,FALSE,FALSE, TRUE, TRUE), -- | 1 | 
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE), -- | Z | 
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE), -- | W | 
(FALSE,FALSE, TRUE,FALSE,FALSE,FALSE, TRUE,FALSE, TRUE), -- | L | 
(FALSE,FALSE,FALSE, TRUE,FALSE,FALSE,FALSE, TRUE, TRUE), -- | H | 
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE));-- | - |

Thus, for example (notice we need type conversions):

IM_TRUE = STD_MATCH(STD_LOGIC_VECTOR    ("10HLXWZ-"), 
                    STD_LOGIC_VECTOR    ("HL10----"))    -- is TRUE

The following code is similar to the first simple example of Section 10.1, but illustrates the use of the Std_Logic_1164 and NUMERIC_STD packages:

entity Counter_1 is end;
        library STD; use STD.TEXTIO.all        library IEEE; use IEEE.STD_LOGIC_1164.all;
use work.NUMERIC_STD.allarchitecture Behave_2 of Counter_1 is 
        signal Clock : STD_LOGIC := '0'; 
        signal Count : UNSIGNED (2 downto 0) := "000";
        begin 
        process begin
                wait for 10 ns; Clock <= not Clock; 
                if (now > 340 ns) then wait;
                end if;
        end process;
        process begin 
                wait until (Clock = '0');
                if (Count = 7) 
                        then Count <= "000"; 
                        else Count <= Count + 1; 
                end if;
        end process;
        process (Count) variable L: LINE; begin write(L, now); 
        write(L, STRING'(" Count=")); write(L, TO_INTEGER(Count)); 
        writeline(output, L); 
        end process;
end;

The preceding code looks similar to the code in Section 10.1 (and the output is identical), but there is more going on here:

  • Line 3 is a library clause and a use clause for the std_logic_1164 package, so you can use the STD_LOGIC type and the NUMERIC_BIT package.
  • Line 4 is a use clause for NUMERIC_BIT package that was previously analyzed into the library work . If the package is instead analyzed into the library IEEE , you would use the name IEEE.NUMERIC_BIT.all here. The NUMERIC_BIT package allows you to use the type UNSIGNED .
  • Line 6 declares Clock to be type STD_LOGIC and initializes it to '0' , instead of the default initial value STD_LOGIC'LEFT (which is 'U' ).
  • Line 7 declares Count to be a 3-bit array of type UNSIGNED from NUMERIC_BIT and initializes it using a bit-string literal.
  • Line 10 uses the overloaded 'not' operator from std_logic_1164 .
  • Line 15 uses the overloaded '=' operator from std_logic_1164 .
  • Line 16 uses the overloaded '=' operator from NUMERIC_BIT .
  • Line 17 requires a bit-string literal, you cannot use Count <= 0 here.
  • Line 18 uses the overloaded '+' operator from NUMERIC_BIT .
  • Line 22 converts Count , type UNSIGNED , to type INTEGER .


1. IEEE Std 1076.3-1997 was approved by the IEEE Standards Board on 20 March 1997. The synthesis package code on the following pages is reprinted with permission from IEEE Std 1076.3-1997, Copyright © 1997 IEEE. All rights reserved. 

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