[ Chapter start ] [ Previous page ] [ Next page ] 5.6 Problems* = Difficult, ** = Very difficult, *** = Extremely difficult 5.1 (Using the ACT 1 Logic Module, 30 min.) Consider the Actel ACT 1 Logic Module shown in Figure 5.1 . Show how to implement: (a) a threeinput NOR gate, (b) a threeinput majority function gate, (c) a 2:1 MUX, (d) a half adder, (e) a threeinput XOR gate, and (f) a fourinput MUX. 5.2 (Worstcase and bestcase timing, 10 min.) Seasoned digital CMOS designers do not worry too much when their designs stop working when they get too hot or when they reduce the supply voltage, but an ASIC that stops working either when increasing the supply voltage above normal or when it gets cold causes panic. Why? 5.3 (Typical to worstcase variation, 10 min.) The 1994 Actel data book (p. 15) remarks that: “the total derating factor from typical to worstcase for a standard ACT 1 array is only 1.19:1, compared to 2:1 for a masked gate array.”
5.4 (ACT 2/3 sequential element, 30 min.). Show how the Actel ACT 2 and ACT 3 sequential element of Figure 5.4 (used in the SModule) can be wired to implement:
5.5 (*ACT 1 logic functions, 40 min.+)
5.6 (Actel and Xilinx, 10 min.) The Actel Logic Modules (ACT 1, ACT 2, and ACT 3) have eight inputs and can implement most threeinput logic functions and a few logic functions with four input variables. In contrast, the Xilinx XC5200 CLB, for example, has only four inputs but can implement all logic functions with four or fewer variables. Why would Actel choose these logic cell designs and how can they be competitive with the Xilinx FPGA (which they are)? 5.7 (Actel address decoders, 10 min.) The maximum number of inputs that the ACT 1 Logic Module can handle is four. The ACT 2/ACT 3 Cmodule increases this to five.
5.8 (Altera shared logic expanders, 30 min.) Consider an Altera MAX 5000 logic array with three productterm lines. You cannot directly implement the function Z = A · B · C + A · B' · C' + A' · B · C' + A' · B' · C with a programmable array logic macrocell that has only three productterm lines, since Z has four product terms.
5.9 (Splitting the XC3000 CLB, 20 min.) In Section 5.2.1 we noted “You can split the (XC3000) 32bit LUT in half, using one of the seven input variables to switch between the F and G outputs. This technique can implement some functions of six and seven variables.”
5.10 (Programmable inversion, 20 min.) Section 5.4 described how the Altera MAX series logic cells can use programmable inversion to reduce the number of product terms needed to implement a function. Give another example of a function of four variables that requires four product terms. Is there a way to tell how many product terms a function may require? 5.11 (Table lookup mapping, 20 min.) Consider a fourinput LUT (used in the CLB in the Xilinx XC2000, the first generation of Xilinx FPGAs, and in the XC5200 LE). This CLB can implement any Boolean function of four variables. Consider the function Z = (A · (B + C)) + (B · D) + (E · F · G · H · I) .(5.27) We can use four CLBs to implement Z as follows: What is the length of the critical path? Find a better assignment in terms of area and critical path. 5.12 (Multiplexer mapping, 10 min.) Consider the function: F = (A · B) + (B' · C) + D .(5.29) Use Shannon’s expansion theorem to expand F wrt B: In other words express F in terms of B, B', F1, and F2 ( Hint: F1 is a function of A and D only, F2 is a function of C and D only). Now expand F1 wrt A, and F2 wrt C. Using your answer, implement F using a single ACT 1 Logic Module. 5.13 (*Xilinx hazards, 10 min.) Explain why the outputs of the Xilinx CLBs are hazardfree for input changes in only one variable. Is this important? 5.14 (**Actel SModules, 10 min.) Notice that CLR is tied to the input corresponding to B0 of the Cmodule in the ACT 2 SModule but the CLR input is separate from the B0 input in the ACT 3 version. Why? 5.15 (**Timing estimates, 60 min.) Using data book values for an FPGA architecture that you choose, and explaining your calculations carefully, estimate the (worstcase commercial) delay for the following functions: (a) 16bit address decoder, (b) 8bit ripplecarry adder, (c) 8bit ripplecarry counter. Give your answers in terms of the data book symbols, and using actual parameters, for a speed grade that you specify, give an example calculation with the delay in ns. 5.16 (Actel logic. 30 min.) Table 5.10 shows how to use the Actel ACT 1 Logic Module to implement some of the 16 functions of two input variables. Complete this table.
5.17 (ACT 1 module implementation, 120 min.)
5.18 (**Xilinx CLB analysis, 60 min.) Table 5.11 shows some information derived from a die photo in the AT&T ATT3000 series data book that shows the eight by eight CLB matrix on an ATT3020 (equivalent to a XC3020) clearly. By measuring the die size in the photo and knowing the actual die size we can calculate the size of a CLB matrix element ( ME ) that includes a single XC3000 CLB as approximately 277 mil^{ 2} . The ME includes interconnect, SRAM, programming, and other resources as well as a CLB.
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