11.15   Problems


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11.15   Problems

* = Difficult, ** = Very difficult, *** = Extremely difficult

11.1 (Counter, 30 min.) Download the VeriWell simulator from http://www. wellspring.com and simulate the counter from Section 11.1 (exclude the comments to save typing). Include the complete input and output listings in your report.

11.2 (Simulator, 30 min.) Build a "cheat sheet" for your simulator, listing the commands for running the simulator and using it in interactive mode.

11.3 (Verilog examples, 10 min.) The Cadence Verilog-XL simulator comes with a directory examples . Make a list of the examples from the README files in the various directories.

11.4 (Gotchas, 60 min.) Build a "most common Verilog mistakes" file. Start with:

  • Extra or missing semicolon ';'
  • Forgetting to declare a reg
  • Using a reg instead of a wire for an input or inout port
  • Bad declarations: reg bus[0:31] instead of reg [31:0]bus
  • Mixing vector declarations: wire [31:0]BusA, [15:0]BusB
  • The case-sensitivity of Verilog
  • No delay in an always statement (simulator loops forever)
  • Mixing up ` (accent grave) for `define and ' (tick or apostrophe) for 1'b1 with ´ (accent acute) or ` (open single quote) or ' (close single quote)
  • Mixing " ( double quote) with " (open quotes) or " (close quotes)

11.5 (Sensitivity, 10 min.) Explore and explain what happens if you write this:

always @(a or b or c) e = (a|b)&(c|d);

11.6 (Verilog if statement, 10 min.) Build test code to simulate the following Verilog fragment. Explain what is wrong and fix the problem.

if (i > 0)
  if (i < 2)  ("i is 1");
else  ("i is less than 0");

11.7 (Effect of delay, 30 min.). Write code to test the four different code fragments shown in Table 11.14 and print the value of 'a' at time = 0 and time = 1 for each case. Explain the differences in your simulation results.

TABLE 11.14    Code fragments for Problem 11.7.

 

(a)

(b)

(c)

(d)

Code fragment

reg a;
initial
begin
a = 0;
a = a + 1;
end
reg a;
initial
begin
#0 a = 0;
#0 a = a + 1;
end
reg a;
initial
begin
a <= 0;
a <= a + 1;
end
reg a;
initial
begin
#1 a = 0;
#1 a = a + 1;
end

11.8 (Verilog events, 10 min.). Simulate the following and explain the results:

event event_1, event_2;
always @ event_1 -> event_2;
initial @event_2 ;
initial -> event_1;

11.9 (Blocking and nonblocking assignment statements, 30 min.). Write code to test the different code fragments shown in Table 11.15 and print the value of 'outp' at time = 0 and time = 10 for each case. Explain the difference in simulation results.

TABLE 11.15    Code fragments for Problem 11.9.

 

(a)

(b)

(c)

(d)

Code fragment

reg outp;
always
begin
#10 outp = 0;
#10 outp = 1;
end
reg outp;
always
begin
outp <= #10 1;
outp <= #10 0;
end
reg outp;
always
begin
#10 outp = 0;
#10 outp <= 1;
end
reg outp;
always
begin
#10 outp <= 0;
#10 outp = 1;
end

11.10 (Verilog UDPs, 20 min.). Use this primitive to build a half adder:

primitive Adder(Sum, InA, InB); output Sum; input Ina, InB;
table 00 : 0; 01 : 1; 10 : 1; 11 : 0; endtable 
endprimitive

Apply unknowns to the inputs. What is the output?

11.11 (Verilog UDPs, 30 min.). Use the following primitive model for a D latch:

primitive DLatch(Q, Clock, Data); output Q; reg Q; input Clock, Data;
table 1 0 : ? : 0; 1 1 : ? : 1; 0 1 : ? : -; endtable 
endprimitive

Check to see what happens when you apply unknown inputs (including clock transitions to unknown). What happens if you apply high-impedance values to the inputs (again including transitions)?

11.12 (Propagation of unknowns in primitives, 45 min.) Use the following primitive model for a D flip-flop:

primitive DFF(Q, Clock, Data); output Q; reg Q; input Clock, Data;
table
r    0 : ? : 0 ;
r    1 : ? : 1 ;
(0x) 0 : 0 : 0 ;
(0x) 1 : 1 : 1 ;
(?0) ? : ? : - ;
? (??) : ? : - ;
endtable 
endprimitive

Check to see what happens when you apply unknown inputs (including a clock transition to an unknown value). What happens if you apply high-impedance values to the inputs (again including transitions)?

11.13 (D flip-flop UDP, 60 min.) Table 11.16 shows a UDP for a D flip-flop with QN output and asynchronous reset and set.

TABLE 11.16    D flip-flop UDP for Problem 11.13.

primitive DFlipFlop2(QN, Data, Clock, Res, Set);
output QN; reg QN; input Data, Clock, Res, Set;
table
//   Data   Clock   Res   Set   :state   :next state
  1  (01)  0  0  :?  :0;  // line 1
  1  (01)  0  x  :?  :0;
  ?  ?  0  x  :0  :0;
  0  (01)  0  0  :?  :1;
  0  (01)  x  0  :?  :1;
  ?  ?  x  0  :1  :1;
  1  (x1)  0  0  :0  :0;
  0  (x1)  0  0  :1  :1;
  1  (0x)  0  0  :0  :0;
  0  (0x)  0  0  :1  :1;
  ?  ?  1  ?  :?  :1;
  ?  ?  0  1  :?  :0;
  ?  n  0  0  :?  :-;
  *  ?  ?  ?  :?  :-;
  ?  ?  (?0)  ?  :?  :-;
  ?  ?  ?  (?0)  :?  :-;
  ?  ?  ?  ?  :?  :x;  // line 17
endtable 
endprimitive

a. Explain the purpose of each line in the truth table.

b. Write a module to test each line of the UDP.

c. Can you find any errors, omissions, or other problems in this UDP?

11.14 (JK flip-flop, 30 min.) Test the following model for a JK flip-flop:

module JKFF (Q, J, K, Clk, Rst);
parameter width = 1, reset_value = 0;
input [width-1:0] J, K; output [width-1:0] Q; reg [width-1:0] Q;
input Clk, Rst; initial Q = {width{1'bx}};
always @ (posedge Clk or negedge Rst )
if (Rst==0 ) Q <= #1 reset_value;
else Q <= #1 (J & ~K) | (J & K & ~Q) | (~J & ~K & Q);
endmodule

11.15 (Overriding Verilog parameters, 20 min.) The following module has a parameter specification that allows you to change the number of AND gates that it models (the cardinality or width):

module Vector_AND(Z, A, B);
  parameter card = 2; input [card-1:0] A,B; output [card-1:0] Z;
  wire [card-1:0] Z = A & B;
endmodule

The next module changes the parameter value by specifying an overriding value in the module instantiation:

module Four_AND_Gates(OutBus, InBusA, InBusB);
  input [3:0] InBusA, InBusB; output [3:0] OutBus;
  Vector_AND #(4) My_AND(OutBus, InBusA, InBusB);
endmodule

These next two modules change the parameter value by using a defparam statement, which overrides the declared parameter value:

module X_AND_Gates(OutBus, InBusA, InBusB);
  parameter X = 2;input [X-1:0] InBusA, InBusB;output [X-1:0] OutBus;
  Vector_AND #(X) My_AND(OutBus, InBusA, InBusB);
endmodule 
module size; defparam X_AND_Gates.X = 4; endmodule

a. Check that the two alternative methods of specifying parameters are equivalent by instantiating the modules Four_AND_Gates and X_AND_Gates in another module and simulating.

b. List and comment on the advantages and disadvantages of both methods.

11.16 (Default Verilog delays, 10 min.). Demonstrate, using simulation, that the following NAND gates have the delays you expect:

nand (strong0, strong1) #1
  Nand_1(n001, n004, n005),
  Nand_2(n003, n001, n005, n002);
nand (n006, n005, n002);

11.17 (Arrays of modules, 30 min.) Newer versions of Verilog allow the instantiating of arrays of modules (in this book we usually call this a vector since we are only allowed one row). You specify the number in the array by using a range after the instance name as follows:

nand #2 nand_array[0:7](zn, a, b);

Create and test a model for an 8-bit register using an array of flip-flops.

11.18 (Assigning Verilog real to integer data types, 10 min.). What is the value of ImInteger in the following code?

real ImReal; integer ImInteger;
initial begin ImReal = -1.5; ImInteger = ImReal; end

11.19 (BNF syntax, 10 min.) Use the BNF syntax definitions in Appendix B to answer the following questions. In each case explain how you arrive at the answer:

a. What is the highest-level construct?

b. What is the lowest-level construct?

c. Can you nest begin and end statements?

d. Where is a legal place for a case statement?

e. Is the following code legal: reg [31:0] rega, [32:1] regb;

f. Where is it legal to include sequential statements?

11.20 (Old syntax definitions, 10 min.) Prior to the IEEE LRM, Verilog BNF was expressed using a different notation. For example, an event expression was defined as follows:

<event_expression> ::= <expression>
  or <<posedge or negedge> <SCALAR_EVENT_EXPRESSION>>
  or <<event_expression> or <event_expression>>

Notice that we are using 'or' as part of the BNF to mean "alternatively" and also ' or ' as a Verilog keyword. The keyword ' or ' is in bold--the difference is fairly obvious. Here is an alternative definition for an event expression:

<event_expression> ::= <expression>
||= posedge <SCALAR_EVENT_EXPRESSION>
||= negedge <SCALAR_EVENT_EXPRESSION>
||= <event_expression> <or <event_expression>>*

Are these definitions equivalent (given, of course, that we replaced ||= with or in the simplified syntax)? Explain carefully how you would attempt to prove that they are the same.

11.21 (Operators, 20 min.) Explain Table 11.17 (see next page).

TABLE 11.17    Unary operators (Problem 11.21).

 

(a)

(b)

(c)

(d)

Code

module unary;
reg [4:0] u;
initial u=!'b011z;
initial ("%b",u);
endmodule
module unary;
wire u;
assign u=!'b011z;
initial  ("%b",u);
endmodule
module unary;
wire u;
assign u=!'b011z;
initial  #1 ("%b",u);
endmodule
module unary;
wire u;
assign u=&'b1;
initial  #1 ("%b",u);
endmodule

Output

0000x
z
x
0

11.22 (Unary reduction, 10 min.) Complete Table 11.18 (see next page).

TABLE 11.18    Unary reduction (Problem 11.22).

Operand

&

~&

|

~|

^

~^

4'b0000

 

 

 

 

 

 

4'b1111

 

 

 

 

 

 

4'b01x0

 

 

 

 

 

 

4'bz000

 

 

 

 

 

 

11.23 (Coerced ports, 20 min.) Perform some experiments to test the behavior of your Verilog simulator in the following situation: "NOTE--A port that is declared as input (output) but used as an output (input) or inout may be coerced to inout. If not coerced to inout, a warning must be issued" [Verilog LRM 12.3.6].

11.24 (*Difficult delay code, 20 min.) Perform some experiments to explain what this difficult to interpret statement does:

#2 a <= repeat(2) @(posedge clk) d;

11.25 (Fork-join, 20 min.) Write some test code to compare the behavior of the code fragments shown in Table 11.19.

TABLE 11.19    Fork-and-join examples for Problem 11.25.

 

(a)

(b)

(c)

(d)

Code fragment

fork 
a = b;
b = a;
join 
fork 
a <= b;
b <= a;
join 
fork 
#1 a = b;
#1 b = a;
join 
fork
a = #1 b;
b = #1 a;
join

11.26 (Blocking and nonblocking assignments, 20 min.) Simulate the following code and explain the results:

module nonblocking; reg Y;
  always begin Y <= #10 1;Y <= #20 0;#10; end
  always begin (,,"Y=",Y); #10; end
  initial #100 ;
endmodule

11.27 (*Flip-flop code, 10 min.) Explain why this flip-flop does not work:

module Dff_Res_Bad(D,Q,Clock,Reset);
output Q; input D,Clock,Reset; reg Q; wire D;
always @(posedge Clock) if (Reset !== 1) Q = D; always if (Reset == 1) Q = 0;
end endmodule

11.28 (D flip-flop, 10 min.) Test the following D flip-flop model:

module DFF (D, Q, Clk, Rst);
parameter width = 1,  reset_value = 0;
input [width-1:0] D; output [width-1:0] Q; reg [width-1:0] Q;
input Clk,Rst;
initial Q = {width{1'bx}};
always @ ( posedge Clk or negedge Rst )
if ( Rst == 0 ) Q <= #1 reset_value; else Q <= #1 D;
endmodule

11.29 (D flip-flop with scan, 10 min.) Explain the following model:

module DFFSCAN (D, Q, Clk, Rst, ScEn, ScIn, ScOut);
parameter width = 1,  reset_value = 0;
input [width-1:0] D; output [width-1:0] Q; reg [width-1:0] Q;
input Clk,Rst,ScEn,ScIn; output ScOut;
initial Q = {width{1'bx}};
always @ ( posedge Clk or negedge Rst ) begin
  if ( Rst == 0 )                 Q <= #1 reset_value;
  else if (ScEn)                 Q <= #1 {Q,ScIn};
  else                 Q <= #1 D;
end
assign ScOut=Q[width-1];
endmodule

11.30 (Pads, 30 min.) Test the following model for a bidirectional I/O pad:

module PadBidir (C, Pad, I, Oen); // active low enable
parameter width=1, pinNumbers="", \strength =1, level="CMOS",
pull="none", externalVdd=5;
output [width-1:0] C; inout  [width-1:0] Pad; input  [width-1:0] I;
input Oen;
assign #1 Pad = Oen ? {width{1'bz}} : I;
assign #1 C = Pad;
endmodule

Construct and test a model for a three-state pad from the above.

11.31 (Loops, 15 min.) Explain and correct the problem in the following code:

module Loop_Bad; reg [3:0] i; reg [31:0] DBus;
initial DBus = 0;
initial begin #1; for (i=0; i<=15; i=i+1) DBus[i]=1; end
initial begin
("DBus = %b",DBus); #2; ("DBus = %b",DBus); ;
end endmodule

11.32 (Arithmetic, 10 min.) Explain the following:

integer IntA;
IntA = -12 / 3; // result is -4
IntA = -'d 12 / 3; // result is 1431655761

Determine and explain the values of intA and regA after each assignment statement in the following code:

integer intA; reg [15:0] regA;
intA = -4'd12; regA = intA/3; regA = -4'd12; 
intA = regA/3; intA = -4'd12/3; regA = -12/3;

11.33 (Arithmetic overflow, 30 min.) Consider the following:

reg [7:0] a, b, sum; sum = (a + b) >> 1;

The intent is to add a and b , which may cause an overflow, and then shift sum to keep the carry bit. However, because all operands in the expression are of an 8-bit width, the expression (a + b) is only 8 bits wide, and we lose the carry bit before the shift. One solution forces the expression (a + b) to use at least 9 bits. For example, adding an integer value of 0 to the expression will cause the evaluation to be performed using the bit size of integers [LRM 4.4.2]. Check to see if the following alternatives produce the intended result:

sum = (a + b + 0) >> 1; 
sum = {0,a} + {0,b} >> 1;

11.34 (*Data slip, 60 min.) Table 11.20 shows several different ways to model the connection of a 2-bit shift register. Determine which of these models suffer from data slip. In each case show your simulation results.

TABLE 11.20    Data slip (Problem 11.34).

 

Alternative

Data slip?

1

always @(posedge Clk) begin Q2 = Q1; Q1 = D1; end

 

2

always @(posedge Clk) begin Q1 = D1; Q2 = Q1; end

 

3

always @(posedge Clk) begin Q1 <= #1 D1; Q2 <= #1 Q1; end

 

4

always @(posedge Clk) Q1 = D1; always @(posedge Clk) Q2 = Q1;

Y

5

always @(posedge Clk) Q1 = #1 D1; always @(posedge Clk) Q2 = #1 Q1;

N

6

always @(posedge Clk) #1 Q1 = D1; always @(posedge Clk) #1 Q2 = Q1;

 

7

always @(posedge Clk) Q1 <= D1; always @(posedge Clk) Q2 <= Q1;

 

8

module FF_1 (Clk, D1, Q1); always @(posedge Clk) Q1 = D1; endmodule
module FF_2 (Clk, Q1, Q2); always @(posedge Clk) Q2 = Q1; endmodule

 

9

module FF_1 (Clk, D1, Q1); always @(posedge Clk) Q1 <= D1; endmodule
module FF_2 (Clk, Q1, Q2); always @(posedge Clk) Q2 <= Q1; endmodule

 

11.35 (**Timing, 30 min.) What does a simulator display for the following?

assign p = q; initial begin q = 0; #1 q = 1; (p); end

What is the problem here? Conduct some experiments to illustrate your answer.

11.36 (Port connections, 10 min.) Explain the following declaration:

module test (.a(c), .b(c));

11.37 (**Functions and tasks, 30 min.) Experiment to determine whether invocation of a function (or task) behaves as a blocking or nonblocking assignment.

11.38 (Nonblocking assignments, 10 min.) Predict the output of the following model:

module e1; reg a, b, c;
initial begin a = 0; b = 1; c = 0; end 
always c = #5 ~c; always @(posedge c) begin a <= b; b <= a; end
endmodule 

11.39 (Assignment timing, 20 min.) Predict the output of the following module and explain the timing of the assignments:

module e2; reg a, b, c, d, e, f;
initial begin a = #10 1; b = #2 0; c = #4 1; end 
initial begin d <= #10 1; e <= #2 0; f <= #4 1; end 
endmodule 

11.40 (Swap, 10 min.) Explain carefully what happens in the following code:

module e3; reg a, b;
initial begin a = 0; b = 1; a <= b; b <= a; end 
endmodule

11.41 (*Overwriting, 30 min.) Explain the problem in the following code, determine what happens, and conduct some experiments to explore the problem further:

module m1; reg a;
initial a = 1;
initial begin a <= #4 0; a <= #4 1; end 
endmodule

11.42 (*Multiple assignments, 30 min.) Explain what happens in the following:

module m2; reg r1; reg [2:0] i;
initial begin 
r1 = 0; for (i = 0; i <= 5; i = i+1) r1 <= # (i*10) i[0]; end
endmodule

11.43 (Timing, 30 min) Write a model to mimic the behavior of a traffic light signal. The clock input is 1 MHz. You are to drive the lights as follows (times that the lights are on are shown in parentheses): green (60 s), yellow (1 s), red (60 s).

11.44 (Port declarations, 30 min.) The rules for port declarations are as follows: "The port expression in the port definition can be one of the following:

  • a simple identifier
  • a bit-select of a vector declared within the module
  • a part-select of a vector declared within the module
  • a concatenation of any of the above

Each port listed in the module definition's list of ports shall be declared in the body of the module as an input, output, or inout (bidirectional). This is in addition to any other declaration for a particular port--for example, a reg, or wire. A port can be declared in both a port declaration and a net or register declaration. If a port is declared as a vector, the range specification between the two declarations of a port shall be identical" [Verilog LRM 12.3.2].

Compile the following and comment (you may be surprised at the results):

module stop (); initial #1 ; endmodule
module Outs_1 (a); output [3:0] a; reg [3:0] a;
initial a <= 4'b10xz; endmodule
module Outs_2 (a); output [2:0] a; reg [3:0] a;
initial a <= 4'b10xz; endmodule
module Outs_3 (a); output [3:0] a; reg [2:0] a;
initial a <= 4'b10xz; endmodule
module Outs_4 (a); output [2:0] a; reg [2:0] a;
initial a <= 4'b10xz; endmodule
module Outs_5 (a); output a; reg [3:0] a;
initial a <= 4'b10xz; endmodule
module Outs_6 (a[2:0]); output [3:0] a; reg [3:0] a;
initial a <= 4'b10xz; endmodule
module Outs_7 (a[1]); output [3:0] a; reg [3:0] a;
initial a <= 4'b10xz; endmodule
module Outs_8 (a[1]); output a; reg [3:0] a; 
always a <= 4'b10xz; endmodule

11.45 (Specify blocks, 30 min.)

a. Describe the pin-to-pin timing of the following module. Build a testbench to demonstrate your explanation.

module XOR_spec (a, b, z); input a, b: output z; xor x1 (z, a, b);
specify
  specparam tnr = 1, tnf = 2 specparam tir = 3, tif = 4;
  if ( a)(b => z) = (tir, tif); if ( b)(a => z) = (tir, tif);
  if (~a)(b => z) = (tnr, tnf); if (~b)(a => z) = (tnr, tnf);
endspecify
endmodule 

b. Write and test a module for a 2:1 MUX with inputs A0 , A1 , and sel ; output Z ; and the following delays: A0 to Z : 0.3 ns (rise) and 0.4 ns (fall); A1 to Z : 0.2 ns (rise) and 0.3 ns (fall); sel to Z = 0.5 ns.

11.46 (Design contest, **60 min.) In 1995 John Cooley organized a contest between VHDL and Verilog for ASIC designers. The goal was to design the fastest 9-bit counter in under one hour using Synopsys synthesis tools and an LSI Logic vendor technology library. The Verilog interface is as follows:

module counter (data_in, up, down, clock,
  count_out, carry_out, borrow_out, parity_out);
output [8:0]  count_out;
output carry_out, borrow_out, parity_out;
input  [8:0]  data_in; input clock, up, down;
reg    [8:0]  count_out; reg carry_out,  borrow_out, parity_out;
// Insert your design here. 
endmodule

The counter is positive-edge triggered, counts up with up='1' and down with down='1' . The contestants had the advantage of a predefined testbench with a set of test vectors; you do not. Design a model for the counter and a testbench.

11.47 (Timing checks, ***60 min.+) Flip-flops with preset and clear require more complex timing-check constructs than those described in Section 11.13.3. The following BNF defines a controlled timing-check event:

controlled_timing_check_event ::= timing_check_event_control specify_terminal_descriptor [ &&& timing_check_condition ]
timing_check_condition ::=
  scalar_expression | ~scalar_expression
| scalar_expression == scalar_constant
| scalar_expression === scalar_constant
| scalar_expression != scalar_constant
| scalar_expression !== scalar_constant

The scalar expression that forms the conditioning signal must be a scalar net, or else the least significant bit of a vector net or a multibit expression value is used. The comparisons in the timing check condition may be deterministic (using === , !== , ~ , or no operator) or nondeterministic (using == or != ). For deterministic comparisons, an 'x' result disables the timing check. For nondeterministic comparisons, an 'x' result enables the timing check.

As an example the following unconditioned timing check,

(data, posedge clock, 10);

performs a setup timing check on every positive edge of clock , as was explained in Section 11.13.3. The following controlled timing check is enabled only when clear is high, which is what is required in a flip-flop model, for example.

(data, posedge clock &&& clear, 10);

The next example shows two alternative ways to enable a timing check only when clear is low. The second method uses a nondeterministic operator.

(data,posedge clock &&&(~clear),10); // clear=x disables check
(data,posedge clock &&&(clear==0),10); // clear=x enables check

To perform the setup check only when clear and preset signals are high, you can add a gate outside the specify block, as follows:

and g1(clear_and_preset, clear, set);

A controlled timing check event can then use this clear_and_preset signal:

(data, posedge clock &&& clear_and_preset, 10);

Use the preceding techniques to expand the D flip-flop model, dff_udp, from Section 11.13.3 to include asynchronous active-low preset and clear signals as well as an output, qbar . Use the following module interface:

module dff(q, qbar, clock, data, preset, clear);

11.48 (Verilog BNF, 30 min.) Here is the "old" BNF definition of a sequential block (used in the Verilog reference manuals and the OVI LRM). Are there any differences from the "new" version?

<sequential_block> ::=
  begin <statement>* end
  or
  begin: <block_IDENTIFIER> <block_declaration>*
    <statement>*
  end
<block_declaration> ::= parameter <list_of_param_assignment>;
  or reg <range>? <attribute_decl>*
    <list_of_register_variable>;
  or integer <attribute_decl>* <list_of_register_variable>;
  or real <attribute_decl>* <list_of_variable_IDENTIFIER>;
  or time <attribute_decl>* <list_of_register_variable>;
  or event <attribute_decl>* <list_of_event_IDENTIFIER>;
<statement> ::=
  <blocking_assignment>;
  or <non-blocking_assignment>;
  or if(<expression>) <statement_or_null>
    <else <statement_or_null> >?
  or <case or casez or casex>
    (<expression>) <case item>+ endcase
  or forever <statement>
  or repeat(<expression>) <statement>
  or while(<expression>) <statement>
  or for(<assignment>;
    <expression>; <assignment>) <statement>
  or wait(<expression>) <statement_or_null>
  or disable <task_IDENTIFIER>;
  or disable <block_IDENTIFIER>;
  or force <assignment>; or release <value>;
  or <timing_control> <statement_or_null>
  or -> <event_IDENTIFIER>;
  or <sequential_block> or <parallel_block>
  or <task_enable> or <system_task_enable>

11.49 (Conditional compiler directives, 30 min.) The conditional compiler directives: `define , `ifdef , `else , `endif , and `undef ; work much as in C. Write and compile a module that models an AND gate as 'z = a&b' if the variable behavioral is defined. If behavioral is not defined, then model the AND gate as 'and a1 (z, a, b)'.

11.50 (*Macros, 30 min.) According to the IEEE Verilog LRM [16.3.1] you can create a macro with parameters using `define , as the following example illustrates. This is a particularly difficult area of compliance. Does your software allow the following? You may have to experiment considerably to get this to work. Hint: Check to see if your software is substituting for the macro text literally or if it does in fact substitute for parameters.

`define M_MAX(a, b)((a) > (b) ? (a) : (b))
`define M_ADD(a,b) (a+b)
module macro;
reg m1, m2, m3, s0, s1;
`define var_nand(delay) nand #delay
`var_nand (2) g121 (q21, n10, n11);
`var_nand (3) g122 (q22, n10, n11);
initial begin s0=0; s1=1;
m1 = `M_MAX (s0, s1); m2 = `M_ADD (s0,s1); m3 = s0 > s1 ? s0 : s1;
end
initial #1 (" m1=",m1," m2=",m2," m3=",m3);
endmodule

11.51 (**Verilog hazards, 30 min.) The MTI simulator, VSIM, is capable of detecting the following kinds of Verilog hazards:

  1. WRITE/WRITE: Two processes writing to the same variable at the same time.
  2. READ/WRITE: One process reading a variable at the same time it is being written to by another process. VSIM calls this a READ/WRITE hazard if it executed the read first.
  3. WRITE/READ: Same as a READ/WRITE hazard except that VSIM executed the write first.

For example, the following log shows how to simulate Verilog code in hazard mode for the example in Section 11.6.2:

> vlib work
> vlog -hazards data_slip_1.v
> vsim -c -hazards data_slip_1
...(lines omitted)...
# 100 0   1 1  x
# ** Error: Write/Read hazard detected on Q1 (ALWAYS 3 followed by ALWAYS 4)
#    Time: 150 ns  Iteration: 1  Instance:/
# 150 1   1 1  1
...(lines omitted)...

There are a total of five hazards in the module data_slip_1, four are on Q1, but there is another. If you correct the code as suggested in Section 11.6.2 and run VSIM, you will find this fifth hazard. If you do not have access to MTI's simulator, can you spot this additional read/write hazard? Hint: It occurs at time zero on Clk. Explain.

11.15.1   The Viterbi Decoder

11.52 (Understanding, 20 min.) Calculate the values shown in Table 11.8 if we use 4 bits for the distance measures instead of 3.

11.53 (Testbenches)

a. (30 min.) Write a testbench for the encoder, viterbi_encode, in Section 11.12 and reproduce the results of Table 11.7.

b. (30 min.) Write a testbench for the receiver front-end viterbi_distances and reproduce the results of Table 11.9 (you can write this stand-alone or use the answer to part a to generate the input). Hint: You will need a model for a D flip-flop. The sequence of results is more important than the exact timing. If you do have timing differences, explain them carefully.

11.54 (Things go wrong, 60 min.) Things do not always go as smoothly as the examples in this book might indicate. Suppose you accidentally invert the sense of the reset for the D flip-flops in the encoder. Simulate the output of the faulty encoder with an input sequence X n = 0, 1, 2, 3, ... (in other words run the encoder with the flip-flops being reset continually). The output sequence looks reasonable (you should find that it is Y n = 0, 2, 4, 6, ...). Explain this result using the state diagram of Figure 11.3. If you had constructed a testbench for the entire decoder and did not check the intermediate signals against expected values you would probably never find this error.

11.55 (Subset decoder) Table 11.21 shows the inputs and outputs from the first-stage of the Viterbi decoder, the subset decoder. Calculate the expected output and then confirm your predictions using simulation.

TABLE 11.21    Subset decoder (Problem 11.55).

input

in0

in1

in2

in3

in4

in5

in6

in7

s0

s1

s2

s3

sout0

sout1

sout2

sout3

5

6

7

6

4

1

0

1

4

1

0

1

4

 

 

 

 

4

7

6

4

1

0

1

4

6

0

1

4

1

 

 

 

 

1

1

0

1

4

6

7

6

4

1

0

1

4

 

 

 

 

0

0

1

4

6

7

6

4

1

0

1

4

1

 

 

 

 


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