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Portions from Application-Specific Integrated Circuits Copyright 1997 by Addison Wesley Longman, Inc.


A CMOS transistor (or device) has four terminals: gate , source , drain , and a fourth terminal that we shall ignore until the next section. A CMOS transistor is a switch. The switch must be conducting or on to allow current to flow between the source and drain terminals (using open and closed for switches is confusing—for the same reason we say a tap is on and not that it is closed ). The transistor source and drain terminals are equivalent as far as digital signals are concerned—we do not worry about labeling an electrical switch with two terminals.

We turn a transistor on or off using the gate terminal. There are two kinds of CMOS transistors: n -channel transistors and p -channel transistors. An n -channel transistor requires a logic '1' (from now on I’ll just say a '1') on the gate to make the switch conducting (to turn the transistor on ). A p -channel transistor requires a logic '0' (again from now on, I’ll just say a '0') on the gate to make the switch nonconducting (to turn the transistor off ). The p -channel transistor symbol has a bubble on its gate to remind us that the gate has to be a '0' to turn the transistor on . All this is shown in Figure 2.1(a) and (b).


FIGURE 2.1 CMOS transistors as switches. (a) An n -channel transistor. (b) A p -channel transistor. (c) A CMOS inverter and its symbol (an equilateral triangle and a circle ).

If we connect an n -channel transistor in series with a p -channel transistor, as shown in Figure 2.1(c), we form an inverter . With four transistors we can form a two-input NAND gate (Figure 2.2a). We can also make a two-input NOR gate (Figure 2.2b). Logic designers normally use the terms NAND gate and logic gate (or just gate), but I shall try to use the terms NAND cell and logic cell rather than NAND gate or logic gate in this chapter to avoid any possible confusion with the gate terminal of a transistor.


FIGURE 2.2 CMOS logic. (a) A two-input NAND logic cell. (b) A two-input NOR logic cell. The n -channel and p -channel transistor switches implement the '1's and '0's of a Karnaugh map.

2.1 CMOS Transistors

2.2 The CMOS Process

2.3 CMOS Design Rules

2.4 Combinational Logic Cells

2.5  Sequential Logic Cells

2.6 Datapath Logic Cells

2.7 I/O Cells

2.8 Cell Compilers

2.9 Summary

2.10 Problems

2.11 Bibliography

2.12 References

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