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* = Difficult,** = Very difficult, *** = Extremely difficult
2.1 (Switches, 20 min.) (a) Draw a circuit schematic for a two-way light switch: flipping the switch at the top or bottom of the stairs reverses the state of two light bulbs, one at the top and one at the bottom of the stairs. Your schematic should show and label all the cables, switches, and bulbs. (b) Repeat the problem for three switches and one light in a warehouse.
2.2 (Logic, 10 min.) The queen wished to choose her successor wisely. She blindfolded and then placed a crown on each of her three children, explaining that there were three red and two blue crowns, and they must deduce the color of their own crown. With blindfolds removed the children could see the two other crowns, but not their own. After a while Anne said: "My crown is red." How did she know?
2.3 (Minus signs, 20 min.) The channel charge in an n -channel transistor is negative. (a) Should there not be a minus sign in Eq. 2.5 to account for this? (b) If so, then where in the derivation of Section 2.1 does the minus sign disappear to arrive at Eq. 2.9 for the current in an n -channel transistor? (c) The equations for the current in a p -channel transistor (Eq. 2.15) have the opposite sign to those for an n -channel transistor. Where in the derivation in Section 2.1 does the extra minus sign arise?
2.4 (Transistor curves, 20 min.) Figure 2.34 shows the measured I DS V DS characteristics for a 20/20 n -channel transistor in a 0.3 m m (effective gate length) process from an ASIC foundry. Derive as much information as you can from this figure.
2.5 (Body effect, 20 min). The equations for the drainsource current (2.9, 2.12, and 2.15) do not contain V SB , the source voltage with respect to the bulk, because we assumed that it was zero. This is not true for the n -channel transistor whose drain is connected to the output in a two-input NAND gate, for example. A reverse substrate bias (or back-gate bias; V SB > 0 for an n -channel transistor) makes the bulk act like a second gate (the back gate) and modifies an n -channel transistor threshold voltage as follows:
where V t 0 n is measured with V SB = 0 V; f 0 is called the surface potential; and g (gamma) is the body-effect coefficient (back-gate bias coefficient),
There are several alternative names and symbols for f 0 ("phi," a positive quantity for an n -channel transistor, typically between 0.60.7 V)you may also see f b (for bulk potential) or 2 f F (twice the Fermi potential, a negative quantity). In Eq. 2.68, e Si = e 0 e r = 1.053 ¥ 10 10 Fm 1 is the permittivity of silicon (the permittivity of a vacuum e 0 = 8.85 ¥ 10 12 Fm 1 and the relative permittivity of silicon is e r = 11.7); NA is the acceptor doping concentration in the bulk (for p -type substrate or well ND for the donor concentration in an n -type substrate or well); and C ox is the gate capacitance per unit area given by
Answer: (a) 0.17 V 0.5 (b) 0.501.3 V.
2.6 (Sizing layout, 10 min.) Stating clearly whatever assumptions you make and describing the tools and methods you use, estimate the size (in l ) of the standard cell shown in Figure 1.3. Estimate the size of each of the transistors, giving their channel lengths and widths (stating clearly which is which).
2.7 (CMOS process) (20 min.) Table 2.15 shows the major steps involved in a typical deep submicron CMOS process. There are approximately 100 major steps in the process.
TABLE 2.15 CMOS process steps (Problem 2.7). 1
Answer: (a) Zero. (b) 0.999. (c) 0.9998. (d) 3 years.
2.8 (Stipple patterns, 30 min.)
2.9 (Select, 20 min.) Can you draw a design-rule correct (according to the design rules in Tables 2.72.9) layout with a piece of select that has a minimum width of 2 l (rule 4.4)?
2.10 (*Inverter layout, 60 min.) Using 1/4-inch ruled paper (or similar) draw a minimum-size inverter (W/L = 1 for both p -channel and n -channel transistors). Use a scale of one square to 2 l and the design rules in Table 2.7Table 2.9. Do not use m2 or m3only m1. Draw the nwell, pwell, ndiff, and pdiff layers, but not the implant layers or the active layer. Include connections to the input, output, VDD, and VSS in m1. There must be at least one well connection to each well ( n -well to VDD, and p -well to VSS). Minimize the size of your cell BB. Draw the BB outline and write its size in l 2 on your drawing. Use green diagonal stripes for ndiff, brown diagonal stripes for pdiff, red diagonal stripes for poly, blue diagonal stripes for m1, solid black for contact). Include a key on your drawing, and clearly label the input, output, VDD, and VSS contacts.
2.11 (*AOI221 Layout, 120 min.) Layout the AOI221 shown in Figure 2.13 with the design rules of Tables 2.72.9 and using Figure 1.3 as a guide. Label clearly the m1 corresponding to the inputs, output, VDD bus, and GND (VSS) bus. Remember to include substrate contacts. What is the size of your BB in l 2 ?
2.12 (Resistance, 20 min.)
2.13 (*Layout graphics, 120 min.) Write a tutorial for capturing layout. As an example:
To capture EPSF (encapsulated PostScript format) from Tanner Research's L-Edit for documentation, Macintosh version... Create a black-and-white technology file, use Setup, Layers..., in L-Edit. The method described here does not work well for grayscale or color. Use File, Print..., Destination check button File to print from L-Edit to an EPS (encapsulated PostScript) file. After you choose Save, a dialog box appears. Select Format: EPS Enhanced Mac Preview, ASCII, Level 1 Compatible, Font Inclusion: None. Save the file. Switch to Frame. Create an Anchored Frame. Use File, Import, File... to bring up a dialog box. Check button Copy into Document, select Format: EPSF. Import the EPS file that will appear as a "page image". Grab the graphic inside the Anchored Frame and move the "page image" around. There will be a footer with text on the "page image" that you may want to hide by using the Anchored Frame edges to crop the image.
Your instructions should be precise, concise, assume nothing, and use the names of menu items, buttons and so on exactly as they appear to the user. Most of the layout figures in this book were created using L-Edit running on a Macintosh, with labels added in FrameMaker. Most of the layouts use the Compass layout editor.
2.14 (Transistor resistance, 20 min.) Calculate I DS and the resistance (the DC value V DS / I DS as well as the AC value as appropriate) of long-channel transistors with the following parameters, under the specified conditions. In each case state whether the transistor is in the saturation region, linear region, or off:
(i) n -channel: V t n = 0.5 V, b n = 40 m AV 2 :
V GS = 3.3V: a. V DS = 3.3 V b. V DS = 0.0 V c. V GS = 0.0 V, V DS = 3.3 V
(ii) p -channel: V t p = 0.6 V, b p = 20 m AV 2 :
V GS = 0.0 V: a. V DS = 0.0 V b. V DS = 5.0 V c. V GS = 5.0 V, V DS = 5.0 V
2.15 (Circuit theory, 15 min.) You accidentally created the "inverter" shown in Figure 2.35 on a full-custom ASIC currently being fabricated. Will it work? Your manager wants a yes or no answer. Your group is a little more understanding: You are to make a presentation to them to explain the problems ahead. Prepare two foils as well as a one page list of alternatives and recommendations.
2.16 (Mask resolution, 10 min.) People use LaserWriters to make printed-circuit boards all the time.
2.17 (Lambda, 10 min.) Estimate l
2.18 (Pass-transistor logic, 10 min.)
2.19 (Transistor parameters, 20 min.) Calculate the (a) electron and (b) hole mobility for the transistor parameters given in Section 2.1 if = 80 mA V 2 and = 40 mA V 2 .
Answer: (a) 0.023 m 2 V 1 s 1 .
2.20 (Quantum behavior, 10 min.) The average thermal energy of an electron is approximately k T, where k = 1.38 ¥ 10 23 JK 1 is Boltzmann's constant and T is the absolute temperature in kelvin.
2.21 (Gallium arsenide, 5 min.) The electron mobility in GaAs is about 8500 cm 2 V 1 s 1 ; the hole mobility is about 400 cm 2 V 1 s 1 . If we could make complementary n -channel and p -channel GaAs transistors (the same way that we do in a CMOS process) what would the ratio of a GaAs inverter be to equalize rise and fall times? About how much faster would you expect GaAs transistors to be than silicon for the same transistor sizes?
2.22 (Margaret of Anjou, 5 min.)
2.23 (Logic cell equations, 5 min.) Show that Eq. 2.31, 2.36, and 2.37 are correct.
2.24 (Carry-lookahead equations, 10 min.)
2.25 (OAI cells, 20 min.) Draw a circuit schematic, including transistor sizes, for (a) an OAI321 cell, (b) an AOI321 cell. (c) Which do you think will be larger?
2.26 (**Making stipple patterns) Construct a set of black-and-white, transparent, 8-by-8 stipple patterns for a CMOS process in which we draw both well layers, the active layer, poly, and both diffusion implant layers separately. Consider only the layers up to m1 (but include m1 and the contact layer). One useful tool is the Apple Macintosh Control Panel, 'General Controls,' that changes the Mac desktop pattern.
2.27 (AOI and OAI cells, 10 min.). Draw the circuit schematics for an AOI22 and an OAI22 cell. Clearly label each transistor as on or off for each cell for an input vector of (A1, A2, B1, B2) = (0101).
2.28 (Flip-flops and latches, 10 min.) In no more than 20 words describe the difference between a flip-flop and a latch.
2.29 (**An old argument) Should setup and hold times appear under maximum, minimum, or typical in a data sheet? (From Peter Alfke.)
2.30 (***Setup, 20 min.) "There is no such thing as a setup and hold time, just two setup timesfor a '1' and for a '0'." Comment. (From Clemenz Portmann.)
2.31 (Subtracter, 20 min.) Show that you can rewrite the equations for a full subtracter (Eqs. 2.652.66) to be the same as a full adderexcept that A is inverted in the borrow out equation, as follows:
DIFF = A B BIN = SUM(A, B, BIN)(2.70)
BOUT = NOT(A) · B + NOT(A) · BIN + B · BIN = MAJ(NOT(A), B, CIN)(2.71)
Explain very carefully why we need to connect BIN to VSS. Show that for a subtracter implemented by inverting the B input of an adder and setting CIN = '1', the true overflow for ones' complement or two's complement representations is XOR(CIN[MSB], CIN[MSB 1]). Does this hold for the above subtracter?
2.32 (Complex CMOS cells) Logic synthesis has completely changed the nature of combinational logic design. Synthesis tools like to see a huge selection of cells from which to choose in order to optimize speed or area.
2.33 (**Design rules, 60 min.) A typical set of deep submicron CMOS design rules is shown in Table 2.16. Design rules are often confusing and use the following "buzz-words," perhaps to prevent others from understanding them.
2.34 (ESD, 10 min.)
2.35 (*Stacks in CMOS cells, 60 min.)
2.36 (Duals, 20 min.) Draw the n -channel stack (including device sizes, assuming a ratio of 2) that complements the p -channel stack shown in Figure 2.37.
2.37 (***FPGA conditional-sum adder, days+) A Xilinx application-note (M. Klein, "Conditional sum adder adds 16 bits in 33 ns," Xilinx Application Brief, Xilinx data book, 1992, p. 6-26) describes a 16-bit conditional-sum adder using 41 CLBs in three stages of addition; see also [Sklansky, 1960]. A Xilinx XC3000 or XC4000 CLB can perform any logic function of five variables, or two functions of (the same) four variables. Can you find a solution with fewer CLBs in three stages? Hint: R. P. Halverson of the University of Hawaii produced a solution with 36 CLBs.
2.38 (Encoding, 10 min.) Booth's algorithm was suggested by a shortcut used by operators of decimal calculating machines that required turning a handle. To multiply 5 by 23 you set the levers to 5 and turned the handle three times, change gears and turn twice more.
2.39 (CSD, 20 min.)
1. Depths of layers are in angstroms (negative values are etch depths). For abbreviations used, see Problem 2.7.
2. sp. = space; ov. = overlap; same = same diffusion or implant type; opposite = opposite implant or diffusion type;
diff = p+ or n+; p+ = p+ diffusion; n+ = n+ diffusion; implant = p+ or n+ implant select.
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