B.3  BNF Index

B.3  BNF Index

Table B.1 is an index to the 208 Verilog HDL BNF productions, as defined in Annex A of the 95 LRM. For example, to find the legal positions of wait_statement (rule 207) we look up 207 in Table B.1 and find rule 181 ( statement ), which is in turn referenced by rules 1, 56, 64, 89, 133, 166, and 182. Thus we know a wait statement is legal in the following places: always_construct (1), function_declaration (56), initial_construct (64), loop_statement (89), par_block (a parallel block, 133), seq_block (a sequential block, 166), and anywhere statement_or_null (182) is legal. Turning again to Table B.1 (or using the backward-pointing links in rule 182), we find statement_or_null (rule 182) is legal in the following places: 8 ( case_item ), 18 ( conditional_statement ), 148 ( procedural_timing_control_statement ), 191 ( task_declaration ), and 207 ( wait_statement ).

TABLE B.1  Index to Verilog HDL BNF rules (list of rules that reference a rule).

1

94

43

40

85

155, 156

127

42

169

28, 157

2

4

44

58

86

71, 160, 193

128

171

170

63

3

4

45

58

87

180

129

7, 95

171

138, 183

4

114

46

45, 98, 134

88

15

130

94

172

4, 28, 61, 121

5

19, 52

47

63

89

181

131

93

173

Highest-level

6

181

48

32

90

31, 146

132

79

174

94

7

57, 133, 166, 190

49

7, 95

91

34

133

181

175

81, 127, 128, 152, 178

8

9

50

48, 50

92

93

134

58

176

174

9

181

51

181

93

94

135

58

177

82, 127, 128, 152, 178

10

107

52

See below

94

91

136

58

178

23, 195

11

58

53

42

95

94

137

58

179

87

12

58

54

171

96

91

138

176

180

176

13

198

55

146

97

58

139

80

181

See below

14

13

56

95

98

58

140

42, 171

182

8, 18, 148, 191, 207

15

Not referenced

57

56

99

21, 146

141

12

183

138

16

88, 168

58

94

100

75

142

53, 54, 127, 128

184

36, 149, 150

17

21, 109, 146, 161

59

61

101

See below

143

83

185

36, 149, 150

18

181

60

61

102

92

144

143

186

19

19

See below

61

114

103

55

145

144

187

181

20

33, 74, 139

62

See below

104

201

146

52

188

187

21

19

63

62

105

12

147

181

189

176

22

94

64

94

106

76, 147

148

181

190

191 (See BNF footnote)

23

189

65

200

107

95

149

58

191

95

24

165

66

95, 190

108

77

150

58

192

181

25

53, 127

67

134, 137

109

106, 147

151

58

193

7, 95

26

28

68

57, 95, 203

110

107

152

179

194

23, 195

27

206

69

175

111

165

153

See below

195

189

28

114

70

See below

112

181

154

56

196

23, 195

29

58, 202

71

7, 95

113

189

155

7, 95

197

189

30

22, 58, 107

72

14, 167

114

21, 146

156

7, 95

198

199

31

32

73

24, 40, 41, 72

115

58

157

114

199

34

32

6, 112, 148

74

152

116

58

158

86

200

164

33

29, 30, 31

75

92

117

58

159

89, 147

201

202

34

173

76

22

118

58

160

7, 95, 203

202

94

35

181

77

107

119

121

161

6, 112, 147, 159

203

199

36

22, 58, 107, 202

78

107

120

121

162

163

204

199

37

196

79

129, 130

121

114

163

194

205

19, 52

38

37

80

140

122

75

164

198

206

28, 33, 157, 172

39

53, 127

81

53, 54

123

95, 190, 203

165

164

207

181

40

41

82

53, 54

124

177

166

181

208

47

41

167

83

91

125

14, 111

167

165

 

 

42

138, 183

84

66, 68, 123

126

See below

168

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19

19, 20, 67, 109, 126, 132, 145, 146, 153, 158, 161, 175, 177, 179, 189

52

6, 8, 9, 17, 18, 25, 32, 50, 52, 55, 89, 90, 99, 100, 106, 108, 109, 112, 122, 131, 146, 159, 161, 163, 187, 192, 197, 207

62

21, 35, 48, 49, 50, 51, 55, 56, 67, 69, 78, 84, 85, 91, 93, 100, 101, 102, 103, 104, 108, 109, 113, 124, 126, 132, 133, 143, 145, 146, 158, 161, 166, 179, 188, 191, 192, 199, 200, 202, 204

70

12, 45, 98, 116, 118

101

12, 45, 98, 116, 118, 134, 137, 151

126

12, 45, 98, 116, 118, 151

153

66, 68, 101, 102, 104, 107, 123, 154, 160

181

1, 56, 64, 89, 133, 166, 182

 

 

Table B.2 is a list of the 102 Verilog HDL keywords in the 95 LRM and an index to the rules that reference these keywords. Note the spelling of the keyword scalared (not scalered). For example, to find out how to use the keyword parameter to define a constant, we look up parameter in Table B.2 to find rule 129 ( parameter_declaration ), which includes a reference to section 3.10 of the 95 LRM. The index in this book will also help (the entry for parameter points you to examples in Section 11.2.4, “Numbers,” in this case).

There are many Verilog tools currently available that use many versions of the Verilog language. Most tool vendors explain which of the Verilog constructs are supported; many use the 95 LRM BNF syntax in this explanation.

TABLE B.2  Verilog HDL keywords and index (list of rules that reference a keyword).

always 1

and 115

assign 22, 147

begin 166

buf 117

bufif0 44

bufif1 44

case 9

casex 9

casez 9

cmos 11

deassign 147

default 8

defparam 130

disable 35

edge 37

else 18

end 166

endcase 9

endfunction 56

endmodule 91

endprimitive 199

endspecify 174

endtable 13, 164

endtask 191

event 49

for 89

force 147

forever 89

fork 133

function 56

highz0 36

highz1 36

if 18, 183

ifnone 183

initial 64, 200

inout 66

input 68

integer 71, 154

join 133

large 10

macromodule 96

medium 10

module 96

nand 115

negedge 39, 50, 196

nmos 97

nor 115

not 117

notif0 44

notif1 44

or 50, 115

output 123

parameter 129

pmos 97

posedge 39, 50, 196

primitive 199

pull0 184

pull1 185

pulldown 58

pullup 58

rcmos 11

real 154, 156

realtime 154, 155

reg 160

release 147

repeat 32, 89

rnmos 97

rpmos 97

rtran 136

rtranif0 135

rtranif1 135

scalared 107

small 10

specify 174

specparam 180

strong0 184

strong1 185

supply0 110, 184

supply1 110, 185

table 13, 164

task 191

time 154, 193

tran 136

tranif0 135

tranif1 135

tri 110

tri0 110

tri1 110

triand 110

trior 110

trireg 107

vectored 107

wait 207

wand 110

weak0 184

weak1 185

while 89

wire 110

wor 110

xnor 1115

xor 115


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