[ Order This Book ] More Info: Brief Foreword Preface Summary Table of Contents HDL Chip Design Author: Smith, Douglas J. Cover: Hard cover Pages: 448 List Price: $65.00 Published by Doone Publications Date Published: 06/1996 ISBN: 0965193438 Table of Contents Chapter One: Introduction Introduction ..... 3 ASIC and FPGA devices ..... 3 Top-Down Design Methodology ..... 5 Hardware Description Languages (HDLs) ..... 8 Design Automation Tools ..... 14 HDL support for synthesis ..... 25 Chapter Two: Synthesis Constraint & Optimization Tutorials Introduction ..... 29 Combinational logic optimization ..... 30 A typical design constraint scenario ..... 32 Chapter Three: Language Fundamentals Design Entities ..... 39 VHDL Design Entity ..... 39 Verilog Design Entity ..... 40 Code Structure ..... 41 Declaration statements ..... 41 Concurrent statements ..... 41 Sequential statements ..... 41 Data Types and Data Objects ..... 44 VHDL Data Types ..... 45 VHDL Data Objects ..... 46 Verilog Data Types ..... 47 Verilog Data Objects ..... 47 Expressions ..... 48 Operands ..... 48 Literal Operands ..... 49 Identifier Operands ..... 50 Aggregate Operands (VHDL) ..... 51 Function Call Operands ..... 52 Index & Slice Name Operands ..... 53 Qualified Expression Operands (VHDL) ..... 54 Type Conversion Operands (VHDL) ..... 56 Record & Record Element Operands (VHDL) ..... 57 Operators ..... 59 Overloaded Operators (VHDL) ..... 59 Arithmetic Operators ..... 63 Sign Operators ..... 64 Relational Operators ..... 64 Equality & Inequality Operators ..... 65 Logical Comparison Operators ..... 66 Logical Bit-wise Operators ..... 68 Shift Operators ..... 69 Concatenation & Verilog replication Operators ..... 70 Reduction Operators (Verilog) ..... 70 Conditional Operator (Verilog) ..... 71 Chapter Four: Design/modeling Recommendations, Issues and Techniques Introduction ..... 75 Design and Modeling Recommendations ..... 75 1. Design and process recommendations ..... 75 2. Power reduction recommendations ..... 75 3. Design for test (OFT) and test issues ..... 75 4. Test harnesses recommendations ..... 76 5. General HDL modeling recommendations ..... 76 6. Ensuring simulation accuracy ..... 77 7. Improving simulation speed ..... 77 8. Synthesis modeling recommendations ..... 78 9. Joint simulation and synthesis modeling recommendations ..... 79 Simulation Compilation Issues ..... 79 1. Output and buffer port modes (VHDL) ..... 79 2. Width qualification of unconstrained arrays (VHDL) ..... 80 3.Operators to the left of the assignment operator ..... 80 4. Unconstrained subprogram parameters in reusable models (VHDL) ..... 81 5. Invisible subprograms from separate packages (VHDL) ..... 82 6. Subprogram overloading using type integer and subtype natural (VHDL) ..... 82 7. Concatenation in the expression of a subprogram's formal list (VHDL) ..... 82 Simulation Run Time Issues ..... 83 1. Full sensitivity/event list (VHDL & Verilog) ..... 83 2. Reversing a vectored array direction (VHDL & Verilog) ..... 83 3. True leading edge detection - wait and if (VHDLJ ..... 84 4. Order dependency of concurrent statements ..... 84 Synthesis Compilation Issues ..... 85 1. Non-static data objects and non-static loops (VHDL & Verilog) ..... 85 Joint Simulation and Synthesis Issues ..... 87 1. When to use others (VHDL) and default (Verilog) ..... 87 2. Signal and variable assignments (VHDL) ..... 89 3. Blocking and non-blocking procedural assignments (Verilog) ..... 94 4. Don't care inputs to a case statement (VHDL & Verilog) ..... 96 5. Don't care outputs from a case statement (VHDL & Verilog) ..... 97 6. Comparing vector array types of different width (VHDL) ..... 98 General Modeling Issues ..... 99 1. Using Attrib