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Low-Voltage, Low-Power Digital BiCMOS Circuits : Circuit Design, Comparative Study, and Sensitivity Analysis
Author: Rofail, Samir S. / Yeo, Kiat Seng

Cover: Hard cover
List Price: $73.00
Published by Prentice Hall
Date Published: 07/1999
ISBN: 0130113808


The quest for excellence in integrated circuit and system design for Very Large-Scale Integration (VLSI) has been geared in recent years towards developing innovative techniques and methodologies to achieve low-voltage, minimum power circuits (designs). This, together with the uncompromising constraint of high chip performance, has shaped a new arena in which the Bipolar compatible Complementary Metal Oxide Semiconductor (BiCMOS) technology has found itself gaining growing significance and attracting keen interest. The high momentum developed in the direction of low-voltage low-power has created a trend sustained and fuelled by the strong demand from the field of portable electronics in general, and the mobile communications market in particular. This trend has led many business leaders and market visionaries to predict that the best is yet to come, and the established trend will stay with us for quite a few years.

This book addresses the design of low-voltage, low-power VLSI digital circuits with a focus on the BiCMOS technology. Such focus has been conceived by the need, greatly felt by the authors, to provide an in-depth coverage of the BiCMOS circuit design ideas, the detailed analyses, and the design methodologies backed by experimental data. This focus, in turn, should help students, designers, and researchers gain deeper insights into the circuit design aspects of BiCMOS integrated circuit and further their understanding of the subject.

This book begins with an introductory chapter on the low-voltage, low-power design where light is being shed on some historical facts, the semiconductor process technology, and its evolution throughout the years. Chapter 2 presents a comprehensive description of the BiCMOS process technology. It highlights the various process requirements and techniques for realizing a high-performance BiCMOS technology. A typical submicron BiCMOS process flow, a new lowpower ultra low capacitance BiCMOS process and the future trends in the BiCMOS process technology are illustrated in the same chapter.

Chapter 3 presents and evaluates the main models of the MOS device, highlights the assumptions made in developing each model, and accurately describes its performance in a scaled technology environment. Much coverage is given in this chapter to the analytical and experimental characterization of the sub-half micron MOS devices, the modeling of lateral pnp bipolar transistors in the pMOSFET structures, and the trends and general features of the various device/process parameters of scaled pMOSFETs operating in a hybrid-mode environment. A key highlight of Chapter 3 is the presentation of a methodology to show how to construct a device model, for a given wafer, with the aid of device characterization tools and successfully retrieved experimental data.

Chapter 4 presents an in-depth analysis and the development of a new generation of BiCMOS circuits for present and future VLSI requirements. Circuit design ideas and techniques are explained in detail to show how they are implemented to improve the circuit performance or to propose a novel circuit structure. Much attention is devoted to full-swing BiCMOS circuits and the inherent techniques such as bootstrapping and transient saturation. The Quasi-Complementary BiCMOS, the Schottky BiCMOS/BiNMOS, the high-b BiCMOS, and the feedback BiCMOS circuits are also covered in-depth. This chapter also covers a comparative evaluation of the various BiCMOS circuits and how these circuits are being applied in a low-voltage lowpower environment.

Chapter 5 deals with the sensitivity of the BiCMOS circuit delay time and power dissipation to changes in key device and circuit parameters. This is especially crucial for small technologies and high-performance BiCMOS circuits whereby the circuit speed in particular can be easily affected by adverse effects caused by the reduced dimensions and an increase in the device and process parameters tolerances. This chapter demonstrates a method to calculate the worst case speed degradation for a given set of tolerances for the device and process parameters.

We hope that this book appeals to students, instructors, circuit designers, engineers, and researchers in the area of BiCMOS circuit design, enhances their knowledge of the subject, and stimulates their ambitions to advance the subject to higher elevations.