This is the third version of the book. This version now not only provides VHDL language coverage but design methodology information as well. This version guides the reader through the process of creating a VHDL design, simulating the design, synthesizing the design, placing and routing the design, and using VITAL simulation to verify the final result. The design example in this version has been updated to reflect the new focus on the design methodology.
This book was written to help hardware design engineers learn how to write good VHDL design descriptions. The goal is to provide enough VHDL and design methodology information to enable a designer to quickly write good VHDL designs and be able to verify the results. This book also attempts to bring the designer with little or no knowledge of VHDL to the level of writing complex VHDL descriptions. It is not intended to show every possible construct of VHDL in every possible use but rather to show the designer how to write concise, efficient, and correct VHDL descriptions of hardware designs.
The book is organized into three logical sections. The first section of the book introduces the VHDL language; the second section walks through a VHDL-based design process including simulation, syntheses, place and route, and VITAL simulation; and the third section walks through a design example of a small CPU design from VHDL capture to final gatelevel implementation. A number of appendices containing useful information about the language and examples used throughout the book are included at the back.
VHDL features are introduced one or more at a time in the first section. As each feature is introduced, one or more real examples are given to show how the feature would be used. The first section consists of Chapters 1 through 8, and each chapter introduces a basic description capability of VHDL. Chapter 1 discusses how VHDL design relates to schematic-based design and introduces the basic terms of the language. Chapter 2 describes some of the basic concepts of VHDL including the different delay mechanisms available, how to use instance-specific data, and defines VHDL drivers. Chapter 2 discusses concurrent statements while Chapter 3 introduces VHDL sequential statements. Chapter 4 talks about the wide range of types available for use in a real example. In Chapter 5 the concepts of subprograms and packages are introduced. The different uses for functions are given, as well as the features available in VHDL packages.
Chapter 8 introduces the five kinds of VHDL attributes. Each attribute type has examples describing how to use the specific attribute to the designer's best advantage. Examples are given describing the purpose of each of the attributes.
Chapters 7 and 8 introduce some of the mare advanced VHDL features. Chapter 7 discusses how VHDL configurations can be used to construct and manage complex VHDL designs. Each of the different configuration styles are discussed along with examples showing usage. Chapter 8 introduces more of the VHDL advanced topics with discussions of overloading, user defined attributes, generate statements, and TextIO.
The second section of the book consists of Chapters 9 through 11. Chapters 9 and 10 discuss the synthesis process and how to write synthesizeable designs. These two chapters describe the basics of the synthesis process including how to write synthesizeable VHDL; what is a technology library; what does the synthesis process look like; what are constraints and attributes; and what does the optimization process look like. Chapter 11 discusses the complete high level design flow from VHDL capture through VITAL simulation.
The third section of the book walks through a description of a small CPU design from the VHDL capture through simulation, synthesis, place and route, and VITAL simulation. Chapter 12 describes the top level of the CPU design from a functional point of view. In Chapter 13 the RTL description of the CPU is presented and discussed from a synthesis point of view. Chapter 14 begins with a discussion of VHDL testbenches and how they are used to verify functionality. Chapter 14 finishes the discussion by describing the simulation of the CPU design. In Chapter 15 the verified design is synthesized to a target technology. Chapter 16 takes the synthesized design and places and routes the design to a target device. Chapter 17 begins with a discussion of VITAL and ends with the VITAL simulation of the placed and routed CPU design.
Finally there are four appendices at the end of the book to provide reference information. Appendix A provides the gate level netlists from the vending machine synthesis process in Chapter 12. Appendix B is a listing of the IEEE 1164 STD LOGIC package used throughout the book. Appendix C is a set of useful tables that condense some of the information in the rest of the book into quick reference tables. Finally, Appendix D describes how to read the Bachus-Naur format (BNF) descriptions found in the VHDL Language Reference Manual. I can only hope that you will have as much fun reading this book and working with VHDL as I did in writing it.
Preface