It is developing revolutionary "package-aware chip design(TM)" software to be formally introduced in January 2006 that will allow chip designers to make optimal tradeoffs between the chip layout, wires within the package and printed circuit board (PCB) connections.
"This is a huge problem that has cost many companies millions in chip redesign and, in some extreme cases, a company's collapse," says Kaushik Sheth, Rio Design Automation's chief executive officer (CEO) and co-founder. "Chip design cannot be done in isolation any longer and a comprehensive approach which allows concurrent design methodology for chip, package and system is a must. The EDA industry has ignored this fundamental optimization and automation need. We believe we are fulfilling this need and filling a large void with package-aware chip design software."
The Market
According to a recent package analysis report conducted by a leading semiconductor provider, the pin count per new application specific integrated circuit (ASIC) designs is growing and, with it, the need for an optimized chip-package interface.
While traditional EDA software for chip design is available for simulation and timing/signal integrity analysis, there are only ad hoc efforts for IO, pad and pin floorplanning. Placement and bump planning/assignment are done manually by experts.
Today's chip design tools are not package-aware and designers are unable to meet design requirements for high-speeds interfaces. No EDA tool offers designers a way to manage a chip's integration with the electronic system or help them explore and design an optimal solution using system in package (SIP) or 3D technology.
The Rio Design Automation Solution
Rio Design Automation's package-aware chip design software will automate a formerly manual effort for high-performance, highly integrated, cost-sensitive chips within full system design. It will help to lower the cost of chip design and accelerate the time to market through earlier timing closure and potentially smaller die size.
The software will enable the design of package-aware chips through an exploration feature to test a variety of chip floorplanning options, synthesis for correct by construction design and an optimization capability for IO, bump and pin placement. It will provide interconnect synthesis for the die and package in a unified environment.
Early versions are in limited use with select customers. Software is available for Linux operating systems. More details on the Rio Design Automation solution will be available in January 2006.
The Team
In addition to Kaushik Sheth, executives include Dr. Robi Dutta who serves as chairman and Egino Sarto, chief technology officer. Both are co-founders.
The team is comprised of experienced circuit designers, computer aided design (CAD) methodologists and EDA developers, all of whom work in the corporate headquarters located in Santa Clara, Calif.
Investors
Rio Design Automation has raised a total of $5.25 million in two rounds of financing from Cadence Design Systems Inc. (NYSE: CDN), Magma Design Automation Inc. (Nasdaq: LAVA) and several angel investors.
Remarks Premal Buch, general manager of Magma's Design Implementation Unit: "As the number of I/Os on a chip increases, package-aware chip design is something that can offer quality of results, improved productivity and time-to-market benefits. Our customers, especially those doing flip chip designs, have been looking for a solution that allows them to do prototyping and feasibility analysis based on I/O pads/bump locations. We have been working closely with Rio Design Automation to develop a joint flow that enables our customers to do just that."
About Rio Design Automation
Rio Design Automation is an electronic design automation (EDA) company bridging the gap between the design of high-performance integrated circuits (ICs) and packages, and a chip's integration with the rest of the electronic system. Its revolutionary approach offers chip designers package-aware software to make optimal tradeoffs among the chip layout, wires within the package and PCB connections. Founded in 2003, its investors include Cadence Design Systems Inc. (NYSE: CDN), Magma Design Automation Inc. (Nasdaq: LAVA) and private angel investors. Corporate headquarters is located at: 2901 Tasman Drive, Suite 112, Santa Clara, Calif. 95054. Telephone: (408) 844-8038. Facsimile: (408) 844-8945. Email: info@rio-da.com. Website: http://www.rio-da.com.
Package-Aware Chip Design is a trademark of Rio Design Automation. Rio Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
Contact:
Public Relations for Rio Design Automation Inc. Nanette Collins, 617-437-1822 Email Contact